PHT8N06LT Nexperia

Philips Semiconductors Product specification TrenchMOS transistor PHT8N06LT Logic level FET GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effect power transistor in a plastic envelope suitable for surface V Drain-source voltage 55 V DS mounting. The device features very I Drain current 7.5 A D low on-state resistance and has P Total power dissipation 1.8 W tot integral zener diodes giving ESD T Junction temperature 150 C j protection. It is intended for use in R Drain-source on-state 80 m DS(ON) DC-DC converters and general resistance V = 5 V GS purpose switching applications. PINNING - SOT223 PIN CONFIGURATION SYMBOL PIN DESCRIPTION d 4 1 gate 2 drain g 3 source 4 drain (tab) s 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V Drain-source voltage - - 55 V DS V Drain-gate voltage R = 20 k -55 V DGR GS V Gate-source voltage - - 13 V GS I Drain current (DC) T = 25 C - 7.5 A D sp I Drain current (DC) On PCB in Fig.2 - 3.5 A D T = 25 C amb I Drain current (DC) On PCB in Fig.2 - 2.2 A D T = 100 C amb I Drain current (pulse peak value) T = 25 C - 40 A DM sp P Total power dissipation T = 25 C - 8.3 W tot sp P Total power dissipation On PCB in Fig.2 - 1.8 W tot T = 25 C amb T , T Storage & operating temperature - - 55 150 C stg j ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V Electrostatic discharge capacitor Human body model - 2 kV C voltage (100 pF, 1.5 k) January 1998 1 Rev 1.100Philips Semiconductors Product specification TrenchMOS transistor PHT8N06LT Logic level FET THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R From junction to solder point Mounted on any PCB 12 15 K/W th j-sp R From junction to ambient Mounted on PCB of Fig.17 - 70 K/W th j-amb STATIC CHARACTERISTICS T= 25C unless otherwise specified j SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V Drain-source breakdown V = 0 V I = 0.25 mA 55 - - V (BR)DSS GS D voltage T = -55C 50 - - V j V Gate threshold voltage V = V I = 1 mA 1.0 1.5 2.0 V GS(TO) DS GS D T = 150C 0.6 - - V j T = -55C - - 2.3 V j I Zero gate voltage drain current V = 55 V V = 0 V - 0.05 10 A DSS DS GS T = 150C - - 100 A j I Gate source leakage current V = 5 V - 0.02 1 A GSS GS T = 150C - - 5 A j V Gate source breakdown voltage I = 1 mA 10 - - V (BR)GSS G R Drain-source on-state V = 5 V I = 5 A - 65 80 m DS(ON) GS D resistance T = 150C - - 148 m j DYNAMIC CHARACTERISTICS T = 25C unless otherwise specified mb SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT g Forward transconductance V = 25 V I = 5 A T = 25C 4 - - S fs DS D j Q Total gate charge I = 7 A V = 44 V V = 5 V - 11.2 - nC g(tot) D DD GS Q Gate-source charge - 2.2 - nC gs Q Gate-drain (Miller) charge - 5 - nC gd C Input capacitance V = 0 V V = 25 V f = 1 MHz - 500 650 pF iss GS DS C Output capacitance - 110 135 pF oss C Feedback capacitance - 60 85 pF rss t Turn-on delay time V = 30 V I = 7 A - 10 15 ns d on DD D t Turn-on rise time V = 5 V R = 10 - 30 50 ns r GS G t Turn-off delay time - 30 45 ns d off t Turn-off fall time T = 25C - 30 40 ns f j REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T = -55 to 175C unless otherwise specified j SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I Continuous reverse drain T = 25C - - 7.5 A DR sp current I Pulsed reverse drain current T = 25C - - 40 A DRM sp V Diode forward voltage I = 5 A V = 0 V - 0.85 1.1 V SD F GS t Reverse recovery time I = 5 A -dI /dt = 100 A/s - 38 - ns rr F F Q Reverse recovery charge V = -10 V V = 30 V - 0.2 - C rr GS R January 1998 2 Rev 1.100