74ABT16373BDL,118 NXP

INTEGRATED CIRCUITS 74ABT16373B 16-bit transparent latch (3-State) Product data 2004 Feb 27 Replaces 74ABT16373B/74ABTH16373B of 1998 Feb 27 
   Philips Semiconductors Product data 16-bit transparent latch (3-State) 74ABT16373B FEATURES PIN CONFIGURATION 16-bit transparent latch 1 48 1OE 1E Multiple V and GND pins minimize switching noise CC 2 47 1Q0 1D0 Power-up 3-State 1Q1 3 46 1D1 GND 4 45 GND Live insertion/extraction permitted 1Q2 5 44 1D2 Power-up reset 1Q3 6 43 1D3 3-State output buffers V 7 42 V CC CC Output capability: +64 mA/32 mA 8 41 1Q4 1D4 1Q5 1D5 9 40 I 19 mA maximum CCL GND GND 10 39 Latch-up protection exceeds 500 mA per JEDEC Std 17 1Q6 11 38 1D6 ESD protection exceeds 2000 V per MIL STD 883 Method 3015 1Q7 1D7 12 37 and 200 V per Machine Model 2Q0 2D0 13 36 2Q1 2D1 14 35 DESCRIPTION GND GND 15 34 The 74ABT16373B high-performance BiCMOS device combines 2Q2 16 33 2D2 low static and dynamic power dissipation with high speed and high output drive. 2Q3 2D3 17 32 V 18 31 V The 74ABT16373B device is a dual octal transparent latch coupled CC CC to two sets of eight 3-State output buffers. The two sections of the 2Q4 2D4 19 30 device are controlled independently by Enable (nE) and Output 2Q5 20 29 2D5 Enable (nOE) control gates. 21 28 GND GND The data on each set of D inputs are transferred to the latch outputs 2Q6 22 27 2D6 when the Latch Enable (nE) input is HIGH. The latch remains 23 26 2Q7 2D7 transparent to the data inputs while nE is HIGH, and stores the data 24 25 2OE 2E that is present one set-up time before the HIGH-to-LOW enable transition. SA00379 The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-LOW Output Enable (nOE) controls eight 3-State buffers independent of the latch operation. When nOE is LOW, the latched or transparent data appears at the outputs. When nOE is HIGH, the outputs are in the high-impedance OFF state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA CONDITIONS SYMBOL PARAMETER TYPICAL UNIT T = 25 C; GND = 0 V amb t Propagation delay 2.5 PLH C = 50 pF; V = 5 V ns L CC t Dn to Qn 2.0 PHL C Input capacitance V = 0 V or V 4 pF IN I CC C Output capacitance V = 0 V or V ; 3-State 7 pF OUT O CC I Outputs disabled; V = 5.5 V 500 A CCZ CC QQuiescentuiescent ssuuppppllyy currentcurrent I Outputs low; V = 5.5 V 8 mA CCL CC ORDERING INFORMATION T = 40 C to +85 C amb Package Type number Name Description Version 74ABT16373BDL SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 74ABT16373BDGG TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 2 2004 Feb 27