INTEGRATED CIRCUITS 74ABT273A Octal D-type flip-flop Product specification 1995 Sep 06 IC23 Data Handbook Philips Semiconductors Product specification Octal D-type flip-flop 74ABT273A FEATURES DESCRIPTION Eight edge-triggered D-type flip-flops The 74ABT273A has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) Buffered common clock and Master Reset (MR) inputs load and reset (clear) all flip-flops Buffered asynchronous Master Reset simultaneously. Power-up reset The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to See 74ABT377 for clock enable version the corresponding flip-flops Q output. See 74ABT373 for transparent latch version All outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for See 74ABT374 for 3-State version applications where the true output only is required and the CP and ESD protection exceeds 2000 V per Mil Std 833 Method 3015 and MR are common elements. 200 V per machine model. QUICK REFERENCE DATA CONDITIONS SYMBOL PARAMETER TYPICAL UNIT T = 25C GND = 0V amb t Propagation delay 3.0 PLH C = 50pF V = 5V ns L CC t CP to Qn 3.4 PHL C Input capacitance V = 0V or V 3.5 pF IN I CC I Total supply current Outputs High V =5.5V 150 A CCH CC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic DIP 40C to +85C 74ABT273A N 74ABT273A N SOT146-1 20-Pin plastic SO 40C to +85C 74ABT273A D 74ABT273A D SOT163-1 20-Pin Plastic SSOP Type II 40C to +85C 74ABT273A DB 74ABT273A DB SOT339-1 20-Pin Plastic TSSOP Type I 40C to +85C 74ABT273A PW 7ABT273APW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN SYMBOL NAME AND FUNCTION MR 1 20 V NUMBER CC Q0 2 19 Q7 11 CP Clock pulse input (active rising edge) D0 3 18 D7 3, 4, 7, 8, 13, D0 - D7 Data inputs D1 4 17 D6 14, 17, 18 Q1 5 16 Q6 2, 5, 6, 9, 12, Q0 - Q7 Data outputs Q2 6 15 Q5 15, 16, 19 D2 7 14 D5 1 MR Master Reset input (active-Low) D3 8 13 D4 10 GND Ground (0V) Q3 9 12 Q4 20 V Positive supply voltage GND 10 11 CP CC SA00052 2 1995 Sep 06 853-1774 15704