Philips Semiconductors Product specification 74ABT573A Octal D-type transparent latch (3-State) The 74ABT573A device is an octal transparent latch coupled to FEATURES eight 3-State output buffers. The two sections of the device are 74ABT573A is flow-through pinout version of 74ABT373 controlled independently by Enable (E) and Output Enable (OE) Inputs and outputs on opposite side of package allow easy control gates. The 74ABT573A is functionally identical to the interface to microprocessors 74ABT373 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. 3-State output buffers Common output enable The data on the D inputs are transferred to the latch outputs when Latch-up protection exceeds 500mA per JEDEC Std 17 the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present ESD protection exceeds 2000 V per MIL STD 883 Method 3015 one setup time before the High-to-Low enable transition. and 200 V per Machine Model Power-up 3-State The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The Power-up reset active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. DESCRIPTION When OE is Low, the latched or transparent data appears at the The 74ABT573A high-performance BiCMOS device combines low outputs. When OE is High, the outputs are in the High-impedance static and dynamic power dissipation with high speed and high OFF state, which means they will neither drive nor load the bus. output drive. QUICK REFERENCE DATA CONDITIONS SYMBOL PARAMETER TYPICAL UNIT T = 25C GND = 0V amb t Propagation delay 2.8 PLH C = 50pF V = 5V ns L CC t Dn to Qn 3.3 PHL C Input capacitance V = 0V or V 3 pF IN I CC C Output capacitance Outputs disabled V = 0V or V 6 pF OUT O CC I Total supply current Outputs disabled V =5.5V 100 A CCZ CC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic DIP 40C to +85C 74ABT573A N 74ABT573A N SOT146-1 20-Pin plastic SO 40C to +85C 74ABT573A D 74ABT573A D SOT163-1 20-Pin Plastic SSOP Type II 40C to +85C 74ABT573A DB 74ABT573A DB SOT339-1 20-Pin Plastic TSSOP Type I 40C to +85C 74ABT573A PW 74ABT573APW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN SYMBOL FUNCTION NUMBER 1 OE Output enable input (active-Low) OE 1 20 V 2, 3, 4, 5, CC D0-D7 Data inputs 6, 7, 8, 9 D0 2 19 Q0 19, 18, 17, 3 18 D1 Q1 16, 15, 14, Q0-Q7 Data outputs D2 4 17 13, 12 Q2 5 16 D3 Q3 11 E Enable input (active-High) D4 6 15 Q4 10 GND Ground (0V) D5 7 14 Q5 20 V Positive supply voltage CC D6 8 13 Q6 D7 9 12 Q7 GND 10 11 E SA00185 1 1995 Sep 06 8531455 15703Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A LOGIC SYMBOL (IEEE/IEC) LOGIC SYMBOL 1 EN 11 C1 234 56789 2 19 2D 1 D0 D1 D2 D3 D4 D5 D6 D7 3 18 11 E 4 17 1 OE 5 16 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 6 15 7 14 19 18 17 16 15 14 13 12 8 13 9 12 SA00187 SA00186 FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING MODE OE E Dn REGISTER Q0 Q7 L H L L L Enable and read register L H H H H L l L L Latch and read register L h H H L L X NC NC Hold H L X NC Z Disable outputs H H Dn Dn Z H = High voltage level h = High voltage level one set-up time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low E transition NC= No change X = Dont care Z = High impedance off state = High-to-Low E transition LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D D D D D D D D EQ EQ EQ EQ EQ EQ EQ EQ 11 E 1 OE 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SA00188 1995 Sep 06 2