74ABT574AD,118 NXP

74ABT574A Octal D-type flip-flop 3-state Rev. 2 23 November 2012 Product data sheet 1. General description The 74ABT574A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT574A is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The clock input (CP) and output enable input (OE) control gates, control the two sections of the device independently. The state of each data input (Dn, one set-up time before the Low-to-High clock transition) is transferred to the Q output of the corresponding flip-flop. When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance off state, which means they do not drive or load the bus. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation. 2. Features and benefits 74ABT574A is flow-through pinout version of 74ABT374A Inputs and outputs on opposite side of package allow easy interface to microprocessors 3-State outputs for bus interfacing Power-on 3-state Power-on reset Common output enable Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Live insertion/extraction permitted.74ABT574A NXP Semiconductors Octal D-type flip-flop 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT574AN 40 Cto+85 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74ABT574AD 40 Cto+85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74ABT574ADB 40 Cto+85 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74ABT574APW 40 Cto+85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 4. Functional diagram 11 C1 1 EN 11 2 19 CP 1D 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 OE 1 mna798 mna446 Fig 1. Logic symbol Fig 2. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aah077 Fig 3. Logic diagram 74ABT574A All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 23 November 2012 2 of 16