74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs December 2007 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Features General Description Edge-triggered D-type inputs The ABT374 is an octal D-type flip-flop featuring sepa- rate D-type inputs for each flip-flop and 3-STATE outputs Buffered positive edge-triggered clock for bus-oriented applications. A buffered Clock (CP) and 3-STATE outputs for bus-oriented applications Output Enable (OE) are common to all flip-flops. Output sink capability of 64mA, source capability of 32mA Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50pF and 250pF loads Guaranteed simultaneous switching, noise level and dynamic threshold performance Guaranteed latchup protection High-impedance, glitch-free bus loading during entire power up and power down cycle Nondestructive, hot-insertion capability Ordering Information Package Order Number Number Package Description 74ABT374CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ABT374CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT374 Rev. 1.5.074ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Connection Diagram Pin Descriptions Pin Names Description D D Data Inputs 0 7 CP Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input OE (Active LOW) O O 3-STATE Outputs 0 7 Functional Description Function Table The ABT374 consists of eight edge-triggered flip-flops Inputs Internal Outputs with individual D-type inputs and 3-STATE true outputs. OE CP D Q O Function The buffered clock and buffered Output Enable are com- mon to all flip-flops. The eight flip-flops will store the H H L NC Z Hold state of their individual D inputs that meet the setup and H H H NC Z Hold hold time requirements on the LOW-to-HIGH Clock (CP) H L L Z Load transition. With the Output Enable (OE) LOW, the con- tents of the eight flip-flops are available at the outputs. H H H Z Load When OE is HIGH, the outputs are in a high impedance L L L L Data Available state. Operation of the OE input does not affect the state L H H H Data Available of the flip-flops. L H L NC NC No Change in Data L H H NC NC No Change in Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT374 Rev. 1.5.0 2