74ABT657 Octal transceiver with parity generator/checker 3-state Rev. 03 15 March 2010 Product data sheet 1. General description The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input (pin T/R) determines the direction of the data ow through the bidirectional transceivers. Transmit (active HIGH) enables data from A ports to B ports Receive (active LOW) enables data from B ports to A ports. When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The parity select input (pin ODD/EVEN) allows the user to generate either an odd or even parity output, depending on the system. Pin PARITY is an output from the generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input when receiving from port B to port A port (pin T/R = LOW). In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH inputs on port A. Pin PARITY output goes to the logic state determined by the setting of pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port A is even, pin PARITY output goes LOW, keeping even parity. In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port B is: Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error 2. Features and benets n Combinational functions in one package n Low static and dynamic power dissipation with high speed and high output drive n Output capability: +64 mA and - 32 mA n Power-up 3-state n Latch-up protection exceeds 500 mA per JESD78B class II level A n ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V74ABT657 NXP Semiconductors Octal transceiver with parity generator/checker 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT657D - 40 C to +85 C SO24 plastic small outline package 24 leads body width 7.5 mm SOT137-1 74ABT657DB - 40 C to +85 C SSOP24 plastic shrink small outline package 24 leads body width SOT340-1 5.3 mm 74ABT657PW - 40 C to +85 C TSSOP24 plastic thin shrink small outline package 24 leads body SOT355-1 width 4.4 mm 4. Functional diagram 2 3 4 5 6 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 1 T/R PARITY 13 24 OE ERROR 12 11 ODD/EVEN B0 B1 B2 B3 B4 B5 B6 B7 23 22 21 20 17 16 15 14 001aae826 Fig 1. Logic symbol 1 0 BUS B TO A 0 0 M 1 BUS A TO B 24 1 2 2 HIGH Z 11 G3 EVEN G4 ODD = 2K 1,3 EVEN 13 1,4 ODD 12 0,3 EVEN 0,4 ODD 223 0 2 322 421 520 617 816 915 10 14 001aae827 Fig 2. IEC logic symbol 74ABT657 3 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 15 March 2010 2 of 17