74ALVC164245DG NXP

74ALVC164245 16-bit dual supply translating transceiver; 3-state Rev. 8 15 March 2012 Product data sheet 1. General description The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to V and pins nBn are referenced to V . CC(A) CC(B) In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than V (typical 0.7 V). V V diode CC(B) CC(A) (except in suspend mode). 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range: 3 V port (V ): 1.5 V to 3.6 V CC(A) 5 V port (V ): 1.5 V to 5.5 V CC(B) CMOS low power consumption Direct interface with TTL levels Control inputs voltage range from 2.7 V to 5.5 V Inputs accept voltages up to 5.5 V High-impedance outputs when V or V = 0 V CC(A) CC(B) Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and 40 C to +125 C74ALVC164245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Temperature Package range Name Description Version 74ALVC164245DL 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads; SOT370-1 body width 7.5 mm 74ALVC164245DGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm 74ALVC164245BX 40 C to +125 C HXQFN60 plastic compatible thermal enhanced extremely SOT1134-2 thin quad flat package; no leads; 60 terminals; body 4 6 0.5 mm 4. Functional diagram 2DIR 1DIR 1OE 2OE 2A0 1A0 1B0 2B0 1A1 2A1 1B1 2B1 1A2 2A2 1B2 2B2 1A3 2A3 1B3 2B3 1A4 2A4 1B4 2B4 1A5 2A5 1B5 2B5 1A6 2A6 1B6 2B6 1A7 2A7 1B7 2B7 001aaa789 Fig 1. Logic symbol 74ALVC164245 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 8 15 March 2012 2 of 20