74HC138N NXP

74HC138 74HCT138 3-to-8 line decoder/demultiplexer inverting Rev. 6 28 December 2015 Product data sheet 1. General description The 74HC138 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 138 ICs and one inverter. The 138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC138: CMOS level For 74HCT138: TTL level Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC138D 40 Cto+125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74 HCT138D 74HC138DB 40 Cto+125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT138DB74HC138 74HCT138 Nexperia 3-to-8 line decoder/demultiplexer inverting Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74HC138PW 40 Cto+125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74HCT138PW 74HC138BQ 40 Cto+125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 74HCT138BQ 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram < < < < WR /( < < ( ,7,1* < < < < < < ( < < ( < ( < PQ D PQ Fig 1. Logic symbol Fig 2. Functional diagram < < < < ( < ( < ( < < DH D Fig 3. Logic diagram 74HC HCT138 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 28 December 2015 2 of 18 D ( ( ( (5 (&2 (1 %