MM74HC154N ON Semiconductor

MM74HC154 4-to-16 Line Decoder September 1983 Revised July 2003 MM74HC154 4-to-16 Line Decoder Each output can drive 10 low power Schottky TTL equiva- General Description lent loads, and is functionally and pin equivalent to the The MM74HC154 decoder utilizes advanced silicon-gate 74LS154. All inputs are protected from damage due to CMOS technology, and is well suited to memory address static discharge by diodes to V and ground. CC decoding or data routing applications. It possesses high noise immunity, and low power consumption of CMOS with Features speeds similar to low power Schottky TTL circuits. Typical propagation delay: 21 ns The MM74HC154 have 4 binary select inputs (A, B, C, and D). If the device is enabled these inputs determine which Power supply quiescent current: 80 A one of the 16 normally HIGH outputs will go LOW. Two Wide power supply voltage range: 26V active LOW enables (G1 and G2) are provided to ease Low input current: 1 A maximum cascading of decoders with little or no external logic. Ordering Code: Order Number Package Number Package Description MM74HC154WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC154MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC154N N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Inputs Low Pin Assignments for DIP, SOIC and TSSOP Output G1 G2 DCBA (Note 1) LLLLLL 0 LLLLL H 1 LLLL H L 2 LLLL H H 3 LLL H L L 4 LLL H L H 5 LLL H H L 6 LLL H H H 7 LL H LLL 8 LL H L L H 9 L L HL HL 10 LL H L H H 11 Top View LL H H LL 12 LL H H L H 13 L L HHH L 14 L L HHHH 15 L H XXXX H L XXXX H H XXXX Note 1: All others HIGH 2003 Fairchild Semiconductor Corporation DS005122 www.fairchildsemi.comLogic Diagram www.fairchildsemi.com 2 MM74HC154