74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop January 2008 74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description I reduced by 50% The AC/ACT74 is a dual D-type flip-flop with Asynchro- CC nous Clear and Set inputs and complementary (Q, Q) Output source/sink 24mA outputs. Information at the input is transferred to the out- ACT74 has TTL-compatible inputs puts on the positive edge of the clock pulse. Clock trig- gering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive- going pulse. After the Clock Pulse input threshold volt- age has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S (Set) sets Q to HIGH level D LOW input to C (Clear) sets Q to LOW level D Clear and Set are independent of clock Simultaneous LOW on C and S makes both Q and D D Q HIGH Ordering Information Package Order Number Number Package Description 74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC74, 74ACT74 Rev. 1.6.174AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names Description D , D Data Inputs 1 2 CP , CP Clock Pulse Inputs 1 2 C , C Direct Clear Inputs D1 D2 S , S Direct Set Inputs D1 D2 Q , Q , Q , Q Outputs 1 1 2 2 Truth Table (Each Half) Inputs Outputs S C CP D Q Q D D LH X X HL HL X X LH LL X X H H HH H H L HH L L H HH L X Q Q 0 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q (Q ) = Previous Q (Q) before LOW-to-HIGH Transition of Clock 0 0 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC74, 74ACT74 Rev. 1.6.1 2