BELASIGNA 250 High-Performance Programmable Audio Processing System Introduction BELASIGNA 250 is a complete programmable audio processing www.onsemi.com system, designed specifically for ultralowpower embedded and portable digital audio systems. This highperformance chip builds on the architecture and design of BELASIGNA 200 to deliver exceptional sound quality along with unmatched flexibility. BELASIGNA 250 incorporates a full audio signal chain, from stereo 16bit A/D converters or digital interfaces to accept the signal, through the fully flexible digital processing architecture, to stereo analog linelevel or direct digital power outputs that can connect LFBGA64 7x7 directly to speakers. CASE 566AF BELASIGNA 250 features flexible clocking options and smart power management features including a soft powerdown mode. Two DSP subsystems operate concurrently: the RCore, which is a fully MARKING DIAGRAM software programmable DSP core, and the weighted overlapadd (WOLA) filterbank coprocessor, which is a dedicated, configurable processor that executes timefrequency domain transforms and other XXXXYZZ vector based computations. A full range of other hardwareassisted BELASIGNA features, such as audiotargeted DMA complete the system. 250 0W888002 A comprehensive and easytouse suite of development tools, AAAA handson training and full technical support are available to enable rapid development and introduction of highly differentiated products 0W888002 = Device Code in record time. XXXX = Date Code Y = Assembly Plant Identifier Key Features ZZ = Traceability Code Unique Parallelprocessing Architecture: A Complete DSPbased, AAAA = Country of Assembly Mixedsignal Audio System Consisting of a 16bit Fully Programmable DualHarvard 16bit DSP Core, a Patented, Highresolution Block Floatingpoint WOLA Filterbank Coprocessor, ORDERING INFORMATION and an Input/Output Processor (IOP) along with Several Peripherals See detailed ordering and shipping information in the package and Interfaces which Optimize the Architecture for Audio Processing dimensions section on page 23 of this data sheet. Integrated Converters and Powered Output: Minimize Need for External Components Ultralow Power Consumption: Under 5 mA at 20 MHz to Support Advanced Operations 1.8 V Supply Voltage Smart Power Management: Including Low Current Standby Mode Requiring Only 0.05 mA Flexible Clocking Architecture: Supports Speeds up to 50 MHz 2 Full Range of Configurable Interfaces: Including: I S, PCM, 2 UART, SPI, I C, TWSS, GPIO Excellent Fidelity: 88 dB System Dynamic Range, Exceptionally Low System Noise and Low Group Delay Support for IP Protection: to Prevent Unauthorized Access to Algorithms and Data These Devices are PbFree, BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2018 Rev. 11 B250/DBELASIGNA 250 Figures and Data Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Voltage at any input pin 0.3 2.2 V Operating supply voltage (Note 1) 0.9 2.0 V Operating temperature range (Note 2) 40 85 C Storage temperature range 40 125 C Caution: Class 2 ESD Sensitivity, JESD22A114B (2000 V) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Below 1.05 V audio performance will be degraded. 2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50C. Electrical Performance Specifications The parameters in Table 2 do not vary with WOLA filterbank configuration. The tests were performed at 20C with a clean 1.8 V supply voltage. BELASIGNA 250 was running in high voltage mode (VDDC = 1.8 V). The system clock (SYS CLK) was set to 5.12 MHz and a sampling frequency of 16 kHz was used with MCLK was set to 1.28 MHz. Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part. Table 2. ELECTRICAL SPECIFICATIONS Description Symbol Conditions Min Typ Max Units Screened OVERALL Supply voltage V 0.9 1.8 2.0 V BAT (Note 3) Current consumption I SYS CLK = 1.28 MHz, 650 A BAT sample rate = 16 kHz 5.12 MHz, 16 kHz 1 mA 19.2 MHz, 16 kHz 5 mA 49.152 MHz, 16 kHz 10 mA 49.152 MHz, 48 kHz 13 mA VREG (1 F External Capacitor) Regulated voltage output V 0.95 1.00 1.05 V REG Regulator PSRR V 1 kHz 50 55 dB REG PSRR Load current I 2 mA LOAD Load regulation LOAD 11 20 mV/mA REG Line regulation LINE 2 5 mV/V REG VDBL (1 F External Capacitor) Regulated doubled voltage output VDBL 1.9 2.0 2.1 V Regulator PSRR VDBL 1 kHz 45 50 dB PSRR Load current I 2 mA LOAD Load regulation LOAD 120 200 mV/mA REG Line regulation LINE 5 10 mV/V REG VDDC (1 F External Capacitor) Digital supply voltage output VDDC LV mode (VREG) 0.9 1.0 1.1 V DV mode (VDBL) 1.8 2.0 2.2 V 3. Audio performance will be degraded below 1.05 V. 4. Measured with a = 12 dB input signal. 5. Input stage delay is inversely proportional to sampling frequency. 6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage. www.onsemi.com 2