74HC4024PW,118 NXP

74HC4024 7-stage binary ripple counter Rev. 10 23 November 2018 Product data sheet 1. General description The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Low-power dissipation Complies with JEDEC standard no. 7A CMOS input levels ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V. Specified from -40 C to +80 C and from -40 C to +125 C. 3. Applications Frequency dividing circuits Time delay circuits. 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4024D -40 C to +125 C SO14 plastic small outline package SOT108-1 14 leads body width 3.9 mmNexperia 74HC4024 7-stage binary ripple counter 5. Functional diagram Q6 3 Q5 4 7-STAGE Q4 5 COUNTER Q3 6 CTR7 12 12 Q0 0 Q2 9 1 11 1 11 CP Q1 + Q1 11 9 9 Q2 6 6 Q0 12 CT Q3 2 5 2 5 MR Q4 CT = 0 4 4 Q5 CP MR 3 3 Q6 6 1 2 001aab906 001aab908 001aab907 Fig. 1. Logic symbol Fig. 2. Functional diagram Fig. 3. IEC logic symbol Q Q Q Q Q Q Q FF FF FF FF FF FF FF 1 2 3 4 5 6 7 CP T T T T T T T Q Q Q Q Q Q Q RD RD RD RD RD RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74HC4024 1 14 CP V CC MR 2 13 n.c. 3 12 Q6 Q0 Q5 4 11 Q1 Q4 5 10 n.c. Q3 6 9 Q2 GND 7 8 n.c. 001aab905 Fig. 5. Pin configuration SOT108-1 (SO14) 74HC4024 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 10 23 November 2018 2 / 13