74HC597N,652 NXP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT597 8-bit shift register with input flip-flops December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 8-bit shift register with input ip-ops 74HC/HCT597 FEATURES GENERAL DESCRIPTION 8-bit parallel storage register inputs The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL Shift register has direct overriding load and clear (LSTTL). They are specified in compliance with JEDEC Output capability: standard standard no. 7A. I category: MSI CC The 74HC/HCT597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5V PHL PLH L CC SH to Q 17 20 ns CP ST to Q 25 29 ns CP PL to Q 21 26 ns f maximum clock frequency SH 96 83 MHz max CP C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 29 32 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2