INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT646 Octal bus transceiver/register 3-state September 1993 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Octal bus transceiver/register 3-state 74HC/HCT646 FEATURES clocked into the registers as the appropriate clock (CP and CP ) goes to a HIGH logic level. Output AB BA Independent register for A and B buses enable (OE) and direction (DIR) inputs are provided to Multiplexed real-time and stored data control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in Output capability: bus driver either the A or B register, or in both. The select source I category: MSI CC inputs (S and S ) can multiplex stored and real-time AB BA (transparent mode) data. The direction (DIR) input GENERAL DESCRIPTION determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), A data may The 74HC/HCT646 are high-speed Si-gate CMOS devices be stored in the B register and/or B data may be stored and are pin compatible with low power Schottky TTL in the A register. (LSTTL). They are specified in compliance with JEDEC When an output function is disabled, the input function is standard no. 7A. still enabled and may be used to store and transmit data. The 74HC/HCT646 consist of bus transceiver circuits with Only one of the two buses, A or B, may be driven at a time. 3-state outputs, D-type flip-flops, and control circuitry The 646 is functionally identical to the 648, but has arranged for multiplexed transmission of data directly from non-inverting data paths. the internal registers. Data on the A or B bus will be QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay A , B to B , A C = 15 pF V =5V 11 13 ns PHL PLH n n n n L CC f maximum clock frequency 69 85 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per channel notes 1 and 2 30 33 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. September 1993 2