74HCT4040D NXP

74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 4 20 March 2014 Product data sheet 1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC4040: CMOS level For 74HCT4040: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Applications Frequency dividing circuits Time delay circuits Control counters 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4040N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil); SOT38-1 long body 74HCT4040N 74HC4040D 40 C to +125 C SO16 plastic small outline package; 16 leads; body SOT109-1 width 3.9 mm 74HCT4040D 74HC4040DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm 74HCT4040DB74HC4040; 74HCT4040 NXP Semiconductors 12-stage binary ripple counter Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74HC4040PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT4040PW 74HC4040BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; 74HCT4040BQ body 2.5 3.5 0.85 mm 5. Functional diagram 10 CP T 12-STAGE COUNTER 11 MR C D 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig 1. Functional diagram CTR12 Q0 9 09 10 + Q1 7 7 11 CT = 0 Q2 6 6 Q3 5 5 10 CP Q4 3 3 Q5 2 2 CT Q6 4 4 Q7 13 13 11 MR Q8 12 12 Q9 14 14 Q10 15 15 Q11 1 11 1 001aad585 001aad586 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC_HCT4040 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4 20 March 2014 2 of 20