74LV04BQ NXP

74LV04 Hex inverter Rev. 03 4 December 2007 Product data sheet 1. General description The 74LV04 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC04 and 74HCT04. The 74LV04 provides six inverting buffers. 2. Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV04N - 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74LV04D - 40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LV04DB - 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LV04PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LV04BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package; no leads; 14 terminals; body 2.5 3 0.85 mm74LV04 NXP Semiconductors Hex inverter 4. Functional diagram 1 1 2 1A 1Y 2 1 1 3 4 3 2A 2Y 4 1 5 6 5 3A 3Y 6 1 9 8 9 4A 4Y 8 1 5Y 11 5A 10 11 10 13 6A 6Y 12 1 13 12 A Y mna343 mna342 mna341 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74LV04 terminal 1 index area 2 13 1Y 6A 1A 1 14 V 2A 3 12 6Y CC 1Y 2 13 6A 2Y 4 11 5A 2A 3 12 6Y (1) 3A 5 10 5Y V CC 2Y 4 04 11 5A 3Y 6 9 4A 3A 5 10 5Y 3Y 6 9 4A 001aah094 GND 7 8 4Y 001aac441 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration DIP14, SO14 and (T)SSOP14 Fig 5. Pin conguration DHVQFN14 74LV04_3 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 4 December 2007 2 of 15 7 1 GND 1A 4Y 8 14 V CC