74LV4053BQ,115 NXP

74LV4053 Triple single-pole double-throw analog switch Rev. 5 18 September 2014 Product data sheet 1. General description The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. V and GND are the supply voltage connections for the digital control inputs (Sn and E). CC The V to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can CC swing between V as a positive limit and V as a negative limit. V V may not CC EE CC EE exceed 6 V. For operation as a digital multiplexer/demultiplexer, V is connected to GND EE (typically ground). V and V are the supply voltage connections for the switches. EE SS 2. Features and benefits Optimized for low-voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Low ON resistance: 180 (typical) at V V = 2.0 V CC EE 100 (typical) at V V = 3.0 V CC EE 75 (typical) at V V = 4.5 V CC EE Logic level translation: To enable 3 V logic to communicate with 3 V analog signals Typical break before make built in ESD protection: HBM JESD22-A114-C exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C74LV4053 NXP Semiconductors Triple single-pole double-throw analog switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4053N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74LV4053D 40 C to +125 C SO16 plastic small outline package 16 leads body SOT109-1 width 3.9 mm 74LV4053DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads body SOT338-1 width 5.3 mm 74LV4053PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LV4053BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1 thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram E V CC 6 16 13 1Y1 LOGIC S1 11 12 1Y0 LEVEL DECODER CONVERSION 14 1Z 1 2Y1 LOGIC S2 10 2 2Y0 LEVEL CONVERSION 15 2Z 3 3Y1 LOGIC S3 9 5 3Y0 LEVEL CONVERSION 43Z 87 GND V 001aak341 EE Fig 1. Functional diagram 74LV4053 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 18 September 2014 2 of 27