74LVT273PW,118 NXP

74LVT273 3.3 V octal D-type ip-op Rev. 03 10 September 2008 Product data sheet 1. General description The 74LVT273 is a high-performance BiCMOS product designed for V operation at CC 3.3 V. This device has eight edge-triggered D-type ip-ops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all ip-ops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding ip-ops Q output. All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where only the true output is required and the CP and MR are common elements. 2. Features n Eight edge-triggered D-type ip-ops n Buffered common clock and asynchronous master reset n Input and output interface capability to systems at 5 V supply n TTL input and output switching levels n Input and output interface capability to systems at 5 V supply n Output capability: +64 mA/- 32 mA n Latch-up protection u JESD78 Class II exceeds 500 mA n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs n Live insertion/extraction permitted n Power-up reset n No bus current loading when output is tied to 5 V bus74LVT273 NXP Semiconductors 3.3 V octal D-type ip-op 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT273D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVT273DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LVT273PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVT273BQ - 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad at package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 CP C1 1 R MR 11 3 2 D0 1D Q0 CP 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 MR D7 Q7 1 mna763 mna764 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT273 3 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 10 September 2008 2 of 17