ADC1010S series Single 10-bit ADC 65 Msps, 80 Msps, 105 Msps or 125 Msps CMOS or LVDS DDR digital outputs Rev. 2 28 December 2010 Product data sheet 1. General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1010S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 62 dBFS SFDR, 86 dBc Input bandwidth, 600 MHz Sample rate up to 125 Msps Power dissipation, 430 mW at 80 Msps 10-bit pipelined ADC core Serial Peripheral Interface (SPI) Clock input divided by 2 for less jitter Duty cycle stabilizer Single 3 V supply Fast OuT-of-Range (OTR) detection Flexible input voltage range: 1 V (p-p) to Offset binary, twos complement, gray 2V (p-p) code CMOS or LVDS DDR digital outputs Power-down and Sleep modes Pin compatible with the ADC1410S HVQFN40 package series and the ADC1210S series 3. Applications Wireless and wired broadband Portable instrumentation communications Spectral analysis Imaging systems Ultrasound equipment Software defined radioADC1010S series NXP Semiconductors Single 10-bit ADC CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s Name Description Version ADC1010S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package SOT618-1 no leads 40 terminals body 6 6 0.85 mm ADC1010S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package SOT618-1 no leads 40 terminals body 6 6 0.85 mm ADC1010S080HN/C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package SOT618-1 no leads 40 terminals body 6 6 0.85 mm ADC1010S065HN/C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package SOT618-1 no leads 40 terminals body 6 6 0.85 mm 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1010S ERROR SPI INTERFACE CORRECTION AND DIGITAL PROCESSING OTR CMOS: INP D9 to D0 T/H ADC CORE OUTPUT or INPUT 10-BIT LVDS DDR: DRIVERS STAGE PIPELINED D8 D9 M to D0 D1 M INM D8 D9 P to D0 D1 P CMOS: DAV or OUTPUT LVDS DDR: DRIVERS DAVP DAVM SYSTEM CLOCK INPUT REFERENCE AND PWD STAGE AND DUTY POWER CYCLE CONTROL OE MANAGEMENT CLKP CLKM VCM SENSE REFT VREF REFB 005aaa134 Fig 1. Block diagram ADC1010S SER All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 28 December 2010 2 of 39