ADC1113D125 Dual 11-bit ADC serial JESD204A interface Rev. 3 10 February 2011 Product data sheet 1. General description The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power at a sample rate of 125 Msps. Pipelined architecture and output error correction ensure the ADC1113D125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A format. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up. The device also includes a programmable full-scale SPI to allow flexible input voltage range of 1 V to 2 V (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1113D125 ideal for use in communications, imaging, and medical applications. 2. Features and benefits SNR, 66.5 dBFS SFDR, 86 dBc Input bandwidth, 600 MHz Sample rate: 125 Msps Power dissipation, 1270 mW Clock input divided by 2 for less jitter SPI register programming contribution 3 V, 1.8 V single supplies Duty Cycle Stabilizer (DCS) Flexible input voltage range: High IF capability 1V(p-p)to2V(p-p) Two configurable serial outputs Offset binary, twos complement, gray code Two JESD204A serial outputs Power-down mode and Sleep mode Pin compatible with ADC1613D series, HVQFN56 package ADC1413D series, and ADC1213D series 3. Applications Wireless and wired broadband Portable instrumentation communications Spectral analysis Imaging systems Ultrasound equipment Software defined radioADC1113D125 NXP Semiconductors Dual 11-bit ADC serial JESD204A interface 4. Ordering information Table 1. Ordering information Type number Sampling Package frequency Name Description Version (Msps) ADC1113D125HN/C1 125 HVQFN56 plastic thermal enhanced very thin quad flat package SOT684-7 no leads 56 terminals body 8 8 0.85 mm 5. Block diagram CFG (0 to 3) SDIO SCLK CS ERROR SPI CORRECTION AND SYNCP DIGITAL SYNCN PROCESSING INAP SWING n T/H ADC A CORE INPUT 11-BIT D11 to D0 STAGE PIPELINED OTR INAM SERIALIZER A CMLPA 8-bit 8-bit 10-bit CLOCK INPUT OUTPUT STAGE & DUTY CMLNA BUFFER A CYCLE CONTROL CLKP DLL PLL CLKM ERROR CORRECTION AND DIGITAL SERIALIZER B CMLPB PROCESSING 8-bit 8-bit 10-bit OUTPUT CMLNB OTR BUFFER B INBP T/H ADC B CORE INPUT 11-BIT D11 to D0 STAGE PIPELINED INBM SWING n CLOCK INPUT SYSTEM STAGE & DUTY REFERENCE AND CYCLE CONTROL POWER MANAGEMENT ADC1113D REFBT REFAB SCRAMBLER RESET REFBB REFAT VCMB VCMA SENSE VREF 005aaa165 Fig 1. Block diagram ADC1113D125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 10 February 2011 2 of 41 FRAME ASSEMBLY SCRAMBLER B SCRAMBLER A ENCODER 8-bit/10-bit B ENCODER 8-bit/10-bit A