ADC1115S125 Single 11-bit ADC 125 Msps with input buffer CMOS or LVDS DDR digital outputs Rev. 2 17 December 2010 Product data sheet 1. General description The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in communications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications because of the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range. 2. Features and benefits SNR, 66.5 dBFS SFDR, 86 dBc Input bandwidth, 600 MHz Sample rate up to 125 Msps Power dissipation, 840 mW including analog input buffer 11-bit pipelined ADC core Serial Peripheral Interface (SPI) Clock input divided by 2 for less jitter Duty cycle stabilizer contribution Integrated input buffer Fast OuT-of-Range (OTR) detection Flexible input voltage range: 1 V (p-p) to Offset binary, twos complement, gray 2 V (p-p) code CMOS or LVDS DDR digital outputs Power-down mode and Sleep mode Pin compatible with the ADC1415S HVQFN40 package series, the ADC1215S series and the ADC1015S seriesCLKP CLKM ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC input buffer CMOS or LVDS DDR digital outputs 3. Applications Wireless and wired broadband Spectral analysis communications Portable instrumentation Ultrasound equipment Imaging systems Software defined radio Digital predistortion loop, power amplifier linearization 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s Name Description Version ADC1115S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package SOT618-6 no leads 40 terminals body 6 6 0.85 mm 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1115S ERROR SPI CORRECTION AND DIGITAL PROCESSING OTR CMOS: D10 to D0 INP or S/H ADC CORE LVDS DDR: INPUT OUTPUT INPUT 11-BIT D9 D10 P BUFFER DRIVERS STAGE PIPELINED to D0 D1 P INM D9 D10 M to D0 D1 M CMOS: DAV OUTPUT or LVDS DDR: DRIVERS DAVP DAVM SYSTEM CLOCK INPUT REFERENCE AND PWD STAGE AND DUTY POWER CYCLE CONTROL OE MANAGEMENT VREF REFB VCM SENSE REFT 005aaa146 Fig 1. Block diagram ADC1115S125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 17 December 2010 2 of 38