ADC1212D series Dual 12-bit ADC 65 Msps, 80 Msps, 105 Msps or 125 Msps CMOS or LVDS DDR digital outputs Rev. 2 4 March 2011 Product data sheet 1. General description The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1212D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 70 dBFS Input bandwidth, 600 MHz SFDR, 86 dBc Power dissipation, 855 mW at 80 Msps Sample rate up to 125 Msps Serial Peripheral Interface (SPI) Clock input divided by 2 to reduce jitter Duty cycle stabilizer contribution Single 3 V supply Fast OuT-of-Range (OTR) detection Flexible input voltage range: Offset binary, twos complement, gray 1Vto2V(p-p) code CMOS or LVDS DDR digital outputs Power-down and Sleep modes Pin and software compatible with HVQFN64 package ADC1412D series and ADC1112D125. 3. Applications Wireless and wired broadband Spectral analysis communications Portable instrumentation Ultrasound equipment Imaging systems Software defined radioADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s Name Description Version ADC1212D125HN/C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package SOT804-3 no leads 64 terminals body 9 9 0.85 mm ADC1212D105HN/C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package SOT804-3 no leads 64 terminals body 9 9 0.85 mm ADC1212D080HN/C1 80 HVQFN64 plastic thermal enhanced very thin quad flat package SOT804-3 no leads 64 terminals body 9 9 0.85 mm ADC1212D065HN/C1 65 HVQFN64 plastic thermal enhanced very thin quad flat package SOT804-3 no leads 64 terminals body 9 9 0.85 mm 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1212D ERROR SPI INTERFACE CORRECTION AND DIGITAL PROCESSING OTRA CMOS: INAP DA11 to DA0 T/H ADC CORE OUTPUT or INPUT 12-BIT DRIVERS LVDS/DDR: STAGE PIPELINED DA10 DA11 P to DA0 DA1 P, INAM DA10 DA11 M to DA0 DA1 M CMOS: DAV CLKP CLOCK INPUT or OUTPUT STAGE AND DUTY LVDS/DDR: DRIVERS CYCLE CONTROL CLKM DAVP DAVM CMOS: INBP DB11 to DB0 T/H ADC CORE OUTPUT or INPUT 12-BIT LVDS/DDR: DRIVERS STAGE PIPELINED DB10 DB11 P to DB0 DB1 P, INBM DB10 DB11 M to DB0 DB1 M OTRB ERROR SYSTEM CORRECTION AND REFERENCE AND CTRL DIGITAL POWER PROCESSING MANAGEMENT REFBT REFAB REFBB REFAT VCMB VCMA SENSE VREF 005aaa128 Fig 1. Block diagram ADC1212D SER All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 4 March 2011 2 of 42