Freescale Semiconductor Document Number: DSP56724EC Rev. 2, 3/2009 Data Sheet: Technical Data DSP56724/DSP56725 DSP56724 144-Pin LQFP 20 mm 20 mm Symphony DSP56724/ 0.5 mm pitch DSP56725 Multi-Core Audio DSP56725 80-Pin LQFP Processors 14 mm 14 mm 0.65 mm pitch See Table 19. meeting high MIPs requirements. Legacy peripherals from The Symphony DSP56724/DSP56725 Multi-Core Audio the previous DSP5636x/37x families are included, as are a Processors are part of the DSP5672x family of programmable variety of new modules available in the DSP5672x family. CMOS DSPs, designed using dual DSP56300 24-bit cores. Modules from the DSP56720 are included, such as an The DSP56724 is intended for consumer and professional Asynchronous Sample Rate Converter (ASRC), an Inter-Core audio applications that require high performance for audio Communication (ICC) module, an External Memory processing. In addition, the DSP56724 is ideally suited for Controller (EMC) to support SDRAM (DSP56724 only), and applications that need the capability to expand memory a Sony/Philips Digital Interface (S/PDIF) transceiver. off-chip or to interface to external parallel peripherals. The DSP56724/DSP56725 devices offer up to 250 million Potential applications include A/V receivers, DVD Receivers, instructions per second (MIPs) per core using an internal Home Theater in a Box (HTIB), and professional audio 250 MHz clock. The DSP56724/ DSP56725 products are high equipment including portable recording equipment, musical density CMOS devices with 3.3 V inputs and outputs. instruments, guitar amplifiers and pedals. The DSP56724 offers customers flexibility in their designs by providing a The DSP56724 block diagram is shown in Figure 1 the more cost-effective alternative to the DSP56720 while DSP56725 block diagram is shown in Figure 2. maintaining pin compatibility. NOTE The DSP56725 is intended for automotive and audio applications that require high performance for audio This document contains information on a new product. processing. Potential applications include A/V receivers, Specifications and information herein are subject to change DVD Receivers, Home Theater in a Box (HTIB), and without notice. Finalized specifications may be published automotive amplifiers and entertainment systems. The after further characterization and device qualifications are DSP56725 offers customers flexibility in their designs by completed. providing a more cost-effective alternative to the DSP56721 while maintaining pin compatibility. The DSP56724/DSP56725 devices provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56724/DSP56725 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56724/ DSP56725 device can replace dual-DSP designs, saving costs while This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2009. All rights reserved.Table of Contents 1 Electrical Characteristics .4 1.2.6 JTAG Timing . 30 1.1 Chip-Level Conditions .4 1.2.7 Watchdog Timer Timing 32 1.1.1 Maximum Ratings 4 1.2.8 S/PDIF Timing . 33 1.1.2 Thermal Characteristics 6 1.2.9 EMC Timing SpecificationsDSP56724 . 34 1.1.3 Power Requirements 6 2 Functional Description and Application Information . 39 1.1.4 Power Consumption Considerations 7 3 Ordering Information . 39 1.1.5 DC Electrical Characteristics 8 4 Package Information . 39 1.1.6 AC Electrical Characteristics 9 4.1 Pinout and Package Information . 40 1.1.7 Internal Clocks 9 4.1.1 Pinout for DSP56724 144-Pin Plastic LQFP 1.1.8 External Clock Operation 10 Package 40 1.1.9 Reset, Stop, Mode Select, and Interrupt Timing 11 4.1.2 Pinout for DSP56725 80-Pin Plastic LQFP Package 1.2 Module-Level Specifications .14 41 1.2.1 Serial Host Interface SPI Protocol Timing .15 4.1.3 Pin Multiplexing 41 2 1.2.2 Serial Host Interface (SHI) I C Protocol Timing.21 4.2 144-Pin Package Outline Drawing 42 2 1.2.3 Programming the SHI I C Serial Clock .23 4.3 80-Pin Package Outline Drawing . 44 1.2.4 Enhanced Serial Audio Interface Timing 24 5 Product Documentation . 46 1.2.5 GPIO Timing .29 6 Revision History 46 Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 2 Freescale Semiconductor