Document Number S32K1XX
NXP Semiconductors
Rev. 7, 04/2018
Data Sheet: Advance Information
S32K1XX
S32K1xx Data Sheet
Notes Power management
Low-power Arm Cortex-M4F/M0+ core with
Technical information for the S32K116 and S32K118
excellent energy efficiency
device families is preliminary until these devices
Power Management Controller (PMC) with multiple
achieve qualification.
power modes: HSRUN, RUN, STOP, VLPR, and
Following two are the available attachments with VLPS. Note: CSEc (Security) or EEPROM writes/
Datasheet: erase will trigger error flags in HSRUN mode (112
S32K1xx_Orderable_Part_Number_ List.xlsx MHz) because this use case is not allowed to
S32K1xx_Power_Modes_Configuration.xlsx execute simultaneously. The device will need to
switch to RUN mode (80 Mhz) to execute CSEc
Key Features
(Security) or EEPROM writes/erase.
Operating characteristics Clock gating and low power operation supported on
Voltage range: 2.7 V to 5.5 V specific peripherals.
Ambient temperature range: -40 C to 105 C for
Memory and memory interfaces
HSRUN mode, -40 C to 125 C for RUN mode
Up to 2 MB program flash memory with ECC
Arm Cortex-M4F/M0+ core, 32-bit CPU 64 KB FlexNVM for data flash memory with ECC
Supports up to 112 MHz frequency (HSRUN mode) and EEPROM emulation. Note: CSEc (Security) or
with 1.25 Dhrystone MIPS per MHz EEPROM writes/erase will trigger error flags in
Arm Core based on the Armv7 Architecture and HSRUN mode (112 MHz) because this use case is
Thumb-2 ISA not allowed to execute simultaneously. The device
Integrated Digital Signal Processor (DSP) will need to switch to RUN mode (80 MHz) to
Configurable Nested Vectored Interrupt Controller execute CSEc (Security) or EEPROM writes/erase.
(NVIC) Up to 256 KB SRAM with ECC
Single Precision Floating Point Unit (FPU) Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
Clock interfaces
Up to 4 KB Code cache to minimize performance
4 - 40 MHz fast external oscillator (SOSC)
impact of memory access latencies
48 MHz Fast Internal RC oscillator (FIRC)
QuadSPI with HyperBus support
8 MHz Slow Internal RC oscillator (SIRC)
128 kHz Low Power Oscillator (LPO) Mixed-signal analog
Up to 112 MHz (HSRUN) System Phased Lock Up to two 12-bit Analog-to-Digital Converter
Loop (SPLL) (ADC) with up to 32 channel analog inputs per
Up to 50 MHz DC external square wave input clock module
Real Time Counter (RTC) One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
Debug functionality
Serial Wire JTAG Debug Port (SWJ-DP) combines
Debug Watchpoint and Trace (DWT)
Instrumentation Trace Macrocell (ITM)
Test Port Interface Unit (TPIU)
Flash Patch and Breakpoint (FPB) Unit
Human-machine interface (HMI)
Up to 156 GPIO pins with interrupt functionality
Non-Maskable Interrupt (NMI)
This document contains information on a pre-production product. Specifications
and pre-production information herein are subject to change without notice. Communications interfaces
Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support
and low power availability
Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
Up to three FlexCAN modules (with optional CAN-FD support)
FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.
Safety and Security
Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the
SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will
trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The
device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
128-bit Unique Identification (ID) number
Error-Correcting Code (ECC) on flash and SRAM memories
System Memory Protection Unit (System MPU)
Cyclic Redundancy Check (CRC) module
Internal watchdog (WDOG)
External Watchdog monitor (EWM) module
Timing and control
Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
One 16-bit Low Power Timer (LPTMR) with flexible wake up control
Two Programmable Delay Blocks (PDB) with flexible trigger system
One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
32-bit Real Time Counter (RTC)
Package
32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package
options
16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 7, 04/2018
2 NXP Semiconductors