Document Number S32K1XX
NXP Semiconductors
Rev. 3, 03/2017
Data Sheet: Product Preview
S32K1XX
S32K1xx Data Sheet
Key Features Mixed-signal analog
Up to two 12-bit Analog-to-Digital Converter
Operating characteristics
(ADC) with up to 32 channel analog inputs per
Voltage range: 2.7 V to 5.5 V
module
Ambient temperature range: -40 C to 105 C for
One Analog Comparator (CMP) with internal 8-bit
HSRUN, -40 C to 125 C for RUN
Digital to Analog Converter (DAC)
ARM Cortex-M4F/M0+ core, 32-bit CPU
Debug functionality
Supports up to 112 MHz frequency with 1.25
Serial Wire JTAG Debug Port (SWJ-DP) combines
Dhrystone MIPS per MHz
Debug Watchpoint and Trace (DWT)
ARM Core based on the ARMv7 Architecture and
Instrumentation Trace Macrocell (ITM)
Thumb-2 ISA
Test Port Interface Unit (TPIU)
Integrated Digital Signal Processor (DSP)
Flash Patch and Breakpoint (FPB) Unit
Configurable Nested Vectored Interrupt Controller
(NVIC) Human-machine interface (HMI)
Single Precision Floating Point Unit (FPU) Up to 156 GPIO pins with interrupt functionality
Non-Maskable Interrupt (NMI)
Clock interfaces
4 - 40 MHz fast external oscillator (SOSC) Communications interfaces
48 MHz Fast Internal RC oscillator (FIRC) Up to three Low Power Universal Asynchronous
8 MHz Slow Internal RC oscillator (SIRC) Receiver/Transmitter (LPUART) modules with
128 kHz Low Power Oscillator (LPO) DMA support and low power availability
Up to 112 MHz System Phased Lock Loop (SPLL) Up to three Low Power Serial Peripheral Interface
Up to 50 MHz DC external square wave input clock (LPSPI) modules with DMA support and low power
Real Time Counter (RTC) availability
Up to two Low Power Inter-Integrated Circuit
Power management
(LPI2C) modules with DMA support and low power
Low-power ARM Cortex-M4F/M0+ core with
availability
excellent energy efficiency
Up to three FlexCAN modules (with optional CAN-
Power Management Controller (PMC) with multiple
FD support)
power modes: HSRUN, Run, Stop, VLPR, and
FlexIO module for flexible and high performance
VLPS
serial interfaces
Supports peripheral specific clock gating. Only
specific peripherals remain working in low power Reliability, safety and security
modes. HW Security Engine (CSEc)
Internal watchdog (WDOG)
Memory and memory interfaces
External Watchdog monitor (EWM) module
Up to 2 MB program flash memory with ECC
Error-Correcting Code (ECC) on flash and SRAM
64 KB FlexNVM for data flash memory with ECC
memories
and EEPROM emulation
Cyclic Redundancy Check (CRC) module
Up to 256 KB SRAM with ECC
128-bit Unique Identification (ID) number
Up to 4 KB of FlexRAM for use as SRAM or
System Memory Protection Unit (System MPU)
EEPROM emulation
Up to 4 KB Code cache to minimize performance
impact of memory access latencies
QuadSPI with HyperBus support
This document contains information on a product under development. NXP
reserves the right to change or discontinue this product without notice.
Preliminary Timing and control
Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM)
One 16-bit Low Power Timer (LPTMR) with flexible wake up control
Two Programmable Delay Blocks (PDB) with flexible trigger system
One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
32-bit Real Time Counter (RTC)
I/O and package
32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, MAPBGA-100, 144-pin LQFP, 176-pin LQFP package
options
16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 3, 03/2017
2 Preliminary NXP Semiconductors