GTL2018PW,118 NXP

GTL2018 8-bit LVTTL to GTL transceiver Rev. 2 29 August 2011 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL/GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface. The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs. 2. Features and benefits Operates as an octal GTL /GTL/GTL+ sampling receiver or as an LVTTL to GTL /GTL/GTL+ driver 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input GTL input and output 3.6 V tolerant V adjustable from 0.5 V to 0.5V ref CC Partial power-down permitted Latch-up protection exceeds 100 mA per JESD78 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101 AEC-Q100 compliance available Package offered: TSSOP24 3. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit input capacitance control inputs -2 2.5 pF C i V =3.0Vor0V I C input/output capacitance A port V =3.0Vor0V - 4.6 6 pF io O B port V =V or 0 V - 3.4 4.3 pF O TT GTL V = 0.8 V V =1.2 V ref TT t LOW to HIGH propagation delay An to Bn see Figure 3 -2.8 5 ns PLH t HIGH to LOW propagation delay An to Bn see Figure 3 -3.4 7 ns PHL t LOW to HIGH propagation delay Bn to An see Figure 4 -5.2 8 ns PLH t HIGH to LOW propagation delay Bn to An see Figure 4 -4.9 7 ns PHLGTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 4. Ordering information Table 2. Ordering information T = 40 Cto +85 C. amb Type number Topside mark Package Name Description Version GTL2018PW GTL2018PW TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 1 GTL2018PW/Q900 1 GTL2018PW/Q900 is AEC-Q100 compliant. Contact i2c.support nxp.com for PPAP. 5. Functional diagram GTL2018 & B0 A0 & B1 A1 & B2 A2 & B3 A3 & B4 A4 & B5 A5 & B6 A6 & B7 A7 002aab603 VREF DIR Fig 1. Logic diagram of GTL2018 GTL2018 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 29 August 2011 2 of 16