HEF4017B 5-stage Johnson decade counter Rev. 8 18 November 2011 Product data sheet 1. General description The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH Q1 to Q9 = LOW) independent of the clock inputs (CP0, CP1). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Automatic counter correction Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description Version HEF4017BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4017BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4017B NXP Semiconductors 5-stage Johnson decade counter 4. Functional diagram CP1 13 CP0 14 5-STAGE JOHNSON COUNTER MR 15 Q5-9 DECODING AND OUTPUT CIRCUITRY 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 2 4 7 10 1 5 6 9 11 001aah242 Fig 1. Functional diagram D Q D Q D Q D Q D Q CP1 FF FF FF FF FF 1 2 3 4 5 CP Q CP Q CP Q CP Q CP Q CP0 RD RD RD RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q5-9 001aah243 Fig 2. Logic diagram HEF4017B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 18 November 2011 2 of 18