IP4853CX24/LF,135 NXP

IP4853CX24 SD, MMC and microSD memory card integrated level shifter with PSU, EMI filter and ESD protection Rev. 3 30 September 2010 Product data sheet 1. Product profile 1.1 General description The IP4853CX24 is a device that fully integrates a bidirectional level shifter or voltage translator, ElectroMagnetic Interference (EMI) filter and ElectroStatic Discharge (ESD) protection diodes. It is specifically designed to be used for memory card interfaces such as Secure Digital (SD), microSD and Multi Media Card (MMC) memory cards. The integrated Power Supply Unit (PSU) supplies memory cards with 2.9 V directly from the battery. This enables a 1.8 V operating host-side device (e.g. a processor interface) to communicate with a 2.9 V compliant memory card using its integrated level shifter. Radiation from digital signals in the higher harmonics, close to typical mobile phone frequencies, is suppressed by the EMI filter. The IP4853CX24 is fabricated using monolithic silicon technology in a Wafer Level Chip-Size Package (WLCSP) with 0.4 mm pitch. 1.2 Features and benefits Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen and antimony (Dark Green compliant) Integrated EMI filters Feedback channel for clock synchronization Integrated ESD protection according to IEC 61000-4-2, level 4 WLCSP with 0.4 mm pitch 1.3 Applications SD-memory card, microSD-memory card and MMC interfaces in latest electronic appliances such as: Mobile phone or smart phone Digital camera Card reader in (laptop) computer Appliances requiring one or several of the following features: Level shifting and voltage translation from 1.8 V to 2.9 V and from 2.9 V to 1.8 V ESD protection according to IEC 61000-4-2, level 4 Power supply regulation from battery to 2.9 V card memory voltage EMI filtering Integration of interface-specific biasing resistor networkIP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 2. Pinning information 2.1 Pinning bump A1 IP4853CX24 index area 13524 A B C D E 001aah951 Transparent top view Fig 1. Pin configuration for WLCSP24 package Table 1. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol A1 DATA2 H A2 DIR CMD A3 DIR 0 A4 V A5 DATA2 SD BAT B1 DATA3 H B2 n.c. B3 V B4 VSD B5 DATA3 SD CC C1 CLK IN C2 ENABLE C3 GND C4 GND C5 CLK SD D1 DATA0 H D2 CMD H D3 CD D4 CMD SD D5 DATA0 SD E1 DATA1 H E2 CLK FB E3 DIR 1 3 E4 WP E5 DATA1 SD 2.2 Pin description Table 2. Pin description 1 2 Symbol Pin Type Description DATA2 H A1 I/O data 2 input or output on host side DIR CMD A2 I direction control input for command DIR 0 A3 I direction control input for data 0 V A4 S supply voltage from battery for regulator BAT DATA2 SD A5 I/O data 2 input or output on memory card side DATA3 H B1 I/O data 3 input or output on host side n.c. B2 - not connected V B3 S supply voltage for host-side circuits CC VSD B4 O output supply voltage for memory card DATA3 SD B5 I/O data 3 input or output on memory card side CLK IN C1 I clock signal input IP4853CX24 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 30 September 2010 2 of 21