NXP Semiconductors Document Number: K32L3A Data Sheet: Technical Data Rev. 1, 09/2019 K32L3A K32L3A60VPJ1AT 72 MHz Arm Cortex-M0+/M4F Dual Core Microcontroller with up to 1280 KB Flash and 384 KB SRAM The K32L3A family of devices is an ultra-low-power, dual core solution ideal for applications that require a high performance Cortex-M4F processor to run the application and an efficient Cortex-M0+ to run low power operations such as sensor data collection and perform low level operations that don t need the full power of the M4 core. 176 VFBGA 9 x 9 x 1 mm Pitch 0.5 mm Core Processor Timers Arm Cortex-M4F core up to 72 MHz (high-speed run up to 2 x 6 ch., 2 x 2 ch. Timer PWM Modules (TPM) 72 MHz) for application code 2 x 4 ch. Low Power Programmable Interrupt Arm Cortex-M0+ core up to 72 MHz (high-speed run up to Timer (LPIT) 72 MHz) for low power operations 3 Low Power Timer (LPTMR) Real Time Clock (RTC) Memories One 56-bit Time stamp 1.25 MB program flash memory, 1 MB on the M4F domain and 256 KB on the M0+ domain Security and Integrity 384 KB SRAM, 256 KB on the M4F domain and 128 KB on 80-bit unique identification number per chip the M0+ domain Advanced Flash security and access control 48 KB ROM with built-in bootloader 16-bit or 32-bit Hardware CRC with 32 B system register file and 32 B RTC register file programmable generator polynomial External bus interface (FlexBUS) for off-chip memory Low-power Cryptographic Acceleration Unit expansion (CAU3) supporting AES128/196/256, DES/ 3DES, SHA 256, RSA and ECC PK-256/ Clocks Curve25519 Low-Power Frequency-Locked Loop (LPFLL) True Random Number Generator Range 1: 48 MHz Up to 4 active anti-tamper detection pins Range 2: 72 MHz Internal Resistance-Capacitance Oscillators (IRCs) Analog Fast-Speed IRC (48, 52, 56, 60 MHz) 1 x 12-bit single ended low-power ADC Slow-Speed IRC (8 MHz or 2 MHz) 2 x Low power comparator (LPCMP) each Low Power Oscillator (LPO - 1 kHz) containing a 6-bit DAC and programmable Real Time Clock Oscillator (RTCOSC) reference input System Clock Generation 1 x 12-bit low power digital-to-analog converter (LPDAC) 1 x 1.2V/2.1V dual-range VREF System Dual Direct Memory Access (DMA) controllers with Peripherals asynchronous capability 1 x Universal Serial Bus (USB) 2.0 Full Speed M4F: 16 channels, 64 inputs per channel (FS) controller with integrated hardware M0+: 8 channels, 32 inputs per channel transceiver, 5 V regulator and 2 KB USB RAM NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Two internal Watchdog and one external Watchdog Monitor 1 x 32 ch. FlexIO supporting emulation of Low-leakage wakeup unit UART, I2C, SPI, I2S, Camera IF, LCD RGB, JTAG and Serial Wire Debug, version 2.0, programming and PWM/Waveform generation debug interface with multi-drop capability 4 x low power UART (LPUART) Trace Features for M4F 4 x low power I2C (LPI2C) modules supporting Cross Trigger Interface up to 1 Mbps Embedded Trace Macrocell 4 x 16-bit low power SPI (LPSPI) supporting Trace Port Interface Unit up to 24 Mbps Trace Features for M0+ 1 x EMVSIM module supporting supporting Cross Trigger Interface ISO-7816 protocol Micro Trace Buffer 1 x Serial Audio Interface (SAI) with support for Breakpoint and Watchpoint Unit I2S and AC 97 Nested Vectored Interrupt Controller 1 x Secure Digital Hardware Controller Memory Protection Unit (uSDHC) Extended Resource Domain Controller I/O Power Management 104 General-purpose input/output pins (GPIO) Bypass mode: 1.71 V to 3.6 V Packages Buck DC-DC converter: 2.1 V to 3.6 V 176 VFBGA 9mm x 9mm x 0.86mm, 0.5mm Core voltage bypass: 1.14 V to 1.45 V direct supply to core, pitch, -40 C to 105 C bypassing internal regulator Independent VDDIO1 and VDDIO2 supply: 1.71 V to 3.6 V Independent VBAT(RTC): 1.71 V to 3.6 V Related resources Type Description Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Package drawing Package dimensions are provided in package drawings. 2 K32L3A, Rev. 1, 09/2019 NXP Semiconductors