Document Number: MM912F634 Freescale Semiconductor Rev. 9.0, 6/2015 Technical Data Integrated S12 Based Relay MM912F634 Driver with LIN The MM912F634 is an integrated single package solution integrating an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver. 48-PIN LQFP-EP 48-PIN LQFP 98ASA00173D Features 98ASH00962A 7.0 mm x 7.0 mm 7.0 mm x 7.0 mm 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM AE SUFFIX: Exposed Pad AP SUFFIX: Non-exposed Pad Background debug (BDM) & debug module (DBG) Die to die bus interface for transparent memory mapping On-chip oscillator & two independent watchdogs Low-power modes with cyclic sense & forced wake-up LIN 2.1 physical layer interface with integrated SCI Current sense module with selectable gain Six digital MCU GPIOs shared with SPI (PA50) Reverse battery protected voltage sense module 10-Bit, 15 channel - analog to digital converter (ADC) Two protected low-side outputs to drive inductive loads 16-Bit, four channel - timer module (TIM16B4C) Two protected high-side outputs 8-Bit, two channel - pulse width modulation module (PWM) Chip temperature sensor Six high-voltage / wake-up inputs (L5.0) Hall sensor supply Three low-voltage GPIOs (PB2.0) Integrated voltage regulator(s) MM912F634 1 Battery Sense VSENSE LS1 VS1 Power Supply PGND M Low-Side Drivers VS2 LS2 LIN interface LIN 1 ISENSEH LGND Current Sense Module 1 ADC2p5 ISENSEL ADC Supply AGND HSUP Hall Sensor supply VDD 2.5V Supply EVDD VDDX Hall Sensor Hall Sensor 5V Supply EVDDX PTB0/AD0/RX/TIM0CH0 5V GPI/O with optional PTB1/AD1/TX/TIM0CH1 pull-up (shared with DGND ADC, PWM, Timer, SCI) Digital Ground EVSS PTB2/AD2/PWM/TIM0CH2 EVSSX HS1 12V Light/LED RESET 1 and switch supply Reset HS2 RESET A PA0/MISO PA1/MOSI L0 PA2/SCK 5V digital I/O L1 Analog/Digital Inputs PA3/SS 1 L2 PA4 1 (High Voltage- and Wake L3 PA5 1 Up capable) L4 1 BKGD/MODC L5 Debug and external EXTAL Oscillator XTAL TCLK Analog Test MCU Test TEST TEST A 1) Feature not available in all Analog Options Figure 1. Simplified Application Diagram Freescale Semiconductor, Inc., 2010-2015. All rights reserved.ORDERING INFORMATION 1 Ordering Information Table 1. Ordering Information Temperature Max. Bus Frequency Analog (2) Device Package Flash (kB) RAM (kB) (1) Range (T ) (MHz) (f ) Option A BUSMAX MM912F634DV1AE 1 98ASA00173D, 48-PIN LQFP-EP 20 32 MM912F634DV2AE -40 to 105 C 2 2 MM912F634DV2AP 98ASH00962A, 48-PIN LQFP 16 32 Note: 1. See Table 2. 2. For Tape and Reel orders add R2 to the part suffix (3) Table 2. Analog Options Feature Option 1 Option 2 Current Sense Module YES NO Wake-up Inputs (Lx) L0L5 L0L3 Note: 3. This table only highlights the analog die differences between the derivatives. See Section 4.2.3, Analog Die Option for detailed information. The device part number follows the standard scheme below: MM 9 12 f xxx r t a PP RR Product Category Memory Type MCU Core Memory Size T Temperature Analog Die Package Designator Analog Core/ Revision A Tape & Reel A 1k Range MM Qualified Standard 9 FLASH, OTP 08 HC08 Target (default A) Option AE LQFP48-EP Indicator B 2k SM Custom Device Blank - ROM 12 HC12 I = 0C to 85C (default 1) AP LQFP48 C 4k PM Prototype Device C = -40C to 85C D 8k V = -40C to 105C E 16k M = -40C to 125C F 32k G 48k H 64k I 96k J 128k Figure 2. Part Number Scheme MM912F634 Analog Integrated Circuit Device Data 2 Freescale Semiconductor