LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller up to 64 kB flash and 8 kB SRAM Rev. 9.2 26 March 2014 Product data sheet 1. General description The LPC1110/11/12/13/14/15 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash 2 memory, up to 8 kB of data memory, one Fast-mode Plus I C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. Remark: The LPC111x series consists of the LPC1100 series (parts LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and LPC1100XL series include the power profiles, a windowed watchdog timer, and a configurable open-drain mode. For related documentation, see Section 16 References. 2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Non-Maskable Interrupt (NMI) input selectable from several input sources (LPC1100XL series only). Serial Wire Debug. System tick timer. Memory: 64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB (LPC1114/323), 32 kB (LPC1114/102/201/202/203/301/302/303), 24 kB (LPC1113), 16 kB (LPC1112), 8 kB (LPC1111), or 4 kB (LPC1110) on-chip flash programming memory. 256 byte page erase function (LPC1100XL series only) 8 kB, 4 kB, 2 kB, or 1 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Digital peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. In addition, a configurable open-drain mode is supported on the LPC1100L and LPC1100XL series. GPIO pins can be used as edge and level sensitive interrupt sources. High-current output driver (20 mA) on one pin. 2 High-current sink drivers (20 mA) on two I C-bus pins in Fast-mode Plus (not on LPC1112FDH20/102). Four general purpose counter/timers with up to eight capture inputs and up to 13 match outputs. Programmable WatchDog Timer (WDT) the LPC1100 series only. Programmable windowed WDT on the LPC1100L and LPC1100XL series only. Analog peripherals: 10-bit ADC with input multiplexing among 5, 6, or 8 pins depending on package size. Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package only). 2 2 I C-bus interface supporting full I C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode (not on LPC1112FDH20/102). Clock generation: 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (LPC1100L and LPC1100XL series only.) Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. Power-On Reset (POR). Brownout detect with up to four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single power supply (1.8 V to 3.6 V). Available as LQFP48 package, HVQFN33 package, and TFBGA48 package. LPC111X All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 26 March 2014 2 of 127