LPC122x 32-bit ARM Cortex-M0 microcontroller up to 128 kB flash and 8 kB SRAM Rev. 2 26 August 2011 Product data sheet 1. General description The LPC122x extend NXP s 32-bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation. Benefitting from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher code density compared to common 8/16-bit microcontroller performing typical tasks. The LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers several times the arithmetic performance of software-based libraries, as well as highly deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0 efficiency also helps the LPC122x achieve lower average power for similar applications. The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash memory brings multiple design benefits, such as finer EEPROM emulation, boot-load support from any serial interface and ease of in-field programming with reduced on-chip RAM buffer requirements. The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with 2 output feedback loop, two UARTs, one SSP/SPI interface, one I C-bus interface with Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine, four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate generation, and up to 55 General Purpose I/O (GPIO) pins. 2. Features and benefits Processor core ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high score of over 45 in CoreMark CPU performance benchmark testing, equivalent to 1.51/MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug (SWD). System tick timer. Memory Up to 8 kB SRAM. Up to 128 kB on-chip flash programming memory. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Includes ROM-based 32-bit integer division routines. Clock generation unitLPC122x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator clock, IRC clock, main clock, and Watchdog clock. Real-Time Clock (RTC). Digital peripherals Micro DMA controller with 21 channels. CRC engine. Two UARTs with fractional baud rate generation and internal FIFO. One UART with RS-485 and modem support and one standard UART with IrDA. SSP/SPI controller with FIFO and multi-protocol capabilities. 2 2 I C-bus interface supporting full I C-bus specification and Fast-mode Plus with a 2 data rate of 1 Mbit/s with multiple address recognition and monitor mode. I C-bus pins have programmable glitch filter. Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor, open-drain mode, programmable digital input glitch filter, and programmable input inverter. Programmable output drive on all GPIO pins. Four pins support high-current output drivers. All GPIO pins can be used as edge and level sensitive interrupt sources. Four general purpose counter/timers with four capture inputs and four match outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers). Windowed WatchDog Timer (WWDT) IEC-60335 Class B certified. Analog peripherals One 8-channel, 10-bit ADC. Two highly flexible analog comparators. Comparator outputs can be programmed to trigger a timer match signal or can be used to emulate 555 timer behavior. Power Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via start logic using 12 port pins. Processor wake-up from Deep-power down and Deep-sleep modes via the RTC. Brownout detect with three separate thresholds each for interrupt and forced reset. Power-On Reset (POR). Integrated PMU (Power Management Unit). Unique device serial number for identification. 3.3 V power supply. Available as 64-pin and 48-pin LQFP package. LPC122X All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 26 August 2011 2 of 61