LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller up to 64 kB flash up to 12 kB SRAM USB device USART EEPROM Rev. 3 20 September 2012 Product data sheet 1. General description The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1315/16/17/45/46/47 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller available on the LPC1345/46/47, this series brings unparalleled design flexibility and seamless integration to todays demanding connectivity solutions. The peripheral complement of the LPC1315/16/17/45/46/47 includes up to 64 kB of flash 2 memory, 8 kB or 10 kB of SRAM data memory, one Fast-mode Plus I C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, an 8-channel, 12-bit ADC, and up to 51 general purpose I/O pins. 2. Features and benefits System: ARM Cortex-M3 r2p1 processor, running at frequencies of up to 72 MHz. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Non Maskable Interrupt (NMI) input selectable from several input sources. System tick timer. Memory: Up to 64 kB on-chip flash program memory with a 256 byte page erase function. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash updates via USB supported. Up to 4 kB on-chip EEPROM data memory with on-chip API support. Up to 12 kB SRAM data memory. 16 kB boot ROM with API support for USB API, power control, EEPROM, and flash IAP/ISP.LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Debug options: Standard JTAG test interface for BSDL. Serial Wire Debug. Support for ETM ARM Cortex-M3 debug time stamping. Digital peripherals: Up to 51 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins support programmable glitch filter. Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources. Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. High-current source output driver (20 mA) on one pin (P0 7). High-current sink driver (20 mA) on true open-drain pins (P0 4 and P0 5). Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs. Programmable Windowed WatchDog Timer (WWDT) with a internal low-power WatchDog Oscillator (WDO). Repetitive Interrupt Timer (RI Timer). Analog peripherals: 12-bit ADC with eight input channels and sampling rates of up to 500 kSamples/s. Serial interfaces: USB 2.0 full-speed device controller (LPC1345/46/47) with on-chip ROM-based USB driver library. USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3). Two SSP controllers with FIFO and multi-protocol capabilities. 2 2 I C-bus interface supporting the full I C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode. Clock generation: Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator) with failure detector. 12 MHz high-frequency Internal RC oscillator (IRC) trimmed to 1 % accuracy over the entire voltage and temperature range. The IRC can optionally be used as a system clock. Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output. PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources. A second, dedicated PLL is provided for USB (LPC1345/46/47). Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control: Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Power profiles residing in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call. LPC1315 16 17 45 46 47 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 20 September 2012 2 of 77