LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 MCU up to 1 MB flash and 136 kB SRAM Ethernet, two High-speed USB, LCD, EMC Rev. 5.3 10 January 2020 Product data sheet 1. General description The LPC185x/3x/2x/1x are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC185x/3x/2x/1x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. For additional documentation related to the LPC18xx parts, see Section 17 References. 2. Features and benefits Processor core ARM Cortex-M3 processor (version r2p1), running at CPU frequencies of up to 180 MHz. ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points. Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support. System tick timer. On-chip memory Up to 1 MB on-chip dual bank flash memory with flash accelerator. 16 kB on-chip EEPROM data memory. 136 kB SRAM for code and data use. Multiple SRAM blocks with separate bus access. 64 kB ROM containing boot code and on-chip software drivers. 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use. Clock generation unit NXP Semiconductors LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and voltage (1.5 % accuracy for T = 0 C to 85 C). amb Ultra-low power RTC crystal oscillator. Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL. Clock output. Configurable digital peripherals: State Configurable Timer/PWM (SCTimer/PWM) subsystem on AHB. Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1. Serial interfaces: Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2). One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0). One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1). USB interface electrical test software included in ROM USB stack. Four 550 UARTs with DMA support: one UART with full modem interface one UART with IrDA interface three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification. Up to two C CAN 2.0B controllers with one channel each. Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. 2 One Fast-mode Plus I C-bus interface with monitor mode and with open-drain I/O 2 pins conforming to the full I C-bus specification. Supports data rates of up to 1 Mbit/s. 2 One standard I C-bus interface with monitor mode and standard I/O pins. 2 Two I S interfaces with DMA support, each with one input and one output. Digital peripherals: External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LCD controller with DMA support and a programmable display resolution of up to 1024H 768V. Supports monochrome and color STN panels and TFT color panels supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. SD/MMC card interface. Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves. Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors. LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 5.3 10 January 2020 2 of 156