LPC2290 16/32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface Rev. 03 16 November 2006 Product data sheet 1. General description The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. With its 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, two advanced CAN channels, PWM channels and up to nine external interrupt pins this microcontroller is particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The LPC2290 provides up to 76 GPIOs depending on bus conguration. With a wide range of additional serial communications interfaces, it is also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2290 will apply to devices with and without the /01 sufx. New devices will use the /01 sufx to differentiate from the original devices only when necessary. 2. Features 2.1 Enhancements introduced with LPC2290/01 device n CPU clock up to 72 MHz and 64 kB of on-chip static RAM. n Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original LPC2290. A port pin can be read at any time regardless of its function. n Dedicated result registers for ADC reduce interrupt overhead. n UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake ow-control fully implemented in hardware. n SSP serial controller supporting SPI, 4-wire SSI, and Microwire buses. 2.2 Key features common for LPC2290 and LPC2290/01 n 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package. n 16/64 kB on-chip static RAM. n Serial bootloader using UART0 provides in-system download and programming capabilities. n EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high-speed real-time tracing of instruction execution. n Two interconnected CAN interfaces with advanced acceptance lters. Additional serial 2 interfaces include two UARTs (16C550), Fast I C-bus (400 kbit/s) and two SPIs.LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface n Eight channel 10-bit ADC with conversion time as low as 2.44 s. n Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock (RTC) and watchdog. n Vectored Interrupt Controller (VIC) with congurable priorities and vector addresses. n Congurable external memory interface with up to four banks, each up to 16 MB and 8/16/32-bit data width. n Up to 76 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive external interrupt pins available. n 60/72 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s. n On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. n Power saving modes include Idle and Power-down. n Processor wake-up from Power-down mode via external interrupt. n Individual enable/disable of peripheral functions for power optimization. n Dual power supply: u CPU operating voltage range of 1.65 V to 1.95 V (1.8 V 0.15 V). u I/O power supply range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads. 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC2290FBD144 LQFP144 plastic low prole quad at package SOT486-1 144 leads body 20 20 1.4 mm LPC2290FBD144/01 LQFP144 plastic low prole quad at package SOT486-1 144 leads body 20 20 1.4 mm 3.1 Ordering options Table 2. Ordering options Type number RAM CAN Enhancements Temperature range LPC2290FBD144 16 kB 2 channels None - 40 C to +85 C LPC2290FBD144/01 64 kB 2 channels Higher CPU clock, more - 40 C to +85 C on-chip SRAM, Fast I/Os, improved UARTs, added SSP, upgraded ADC LPC2290 3 NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 16 November 2006 2 of 41