LPC2388 Single-chip 16-bit/32-bit micro 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 3 15 October 2013 Product data sheet 1. General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2388 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with 4 kB of endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial 2 2 Ports (SSP), three I C-bus interfaces, an I S-bus interface, and an External Memory Controller (EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of 64 kB, 16 kB SRAM for Ethernet, 16 kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM make this device very well suited for communication gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO lines with up to 50 edge and up to four level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. Features and benefits ARM7TDMI-S processor, running at up to 72 MHz. Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access. 64 kB of SRAM on the ARM local bus for high performance CPU access. 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. 16 kB SRAM for general purpose DMA use also accessible by the USB. Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem. EMC provides support for static devices such as flash and SRAM as well as off-chip memory mapped peripherals. Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.LPC2388 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP 2 serial interfaces, the I S-bus port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. CAN controller with two channels. SPI controller. Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller. 2 Three I C-bus interfaces (one with open-drain and two with standard port pins). 2 I S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. Other peripherals: SD/MMC memory card interface. 104 General purpose I/O pins with configurable pull-up/down resistors. 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC. Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs. Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock. 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. Standard ARM test/debug interface for compatibility with existing tools. Emulation trace module supports real-time trace. Single 3.3 V power supply (3.0 V to 3.6 V). Four reduced power modes: Idle, Sleep, Power-down and Deep power-down. Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt). Two independent power domains allow fine tuning of power consumption based on needed features. Each peripheral has its own clock divider for further power saving. Brownout detect with separate thresholds for interrupt and forced reset. On-chip power-on reset. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz. LPC2388 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 15 October 2013 2 of 74