LPC3141/3143 Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller Rev. 1 4 June 2012 Product data sheet 1. General description The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features and benefits 2.1 Key features CPU platform 270 MHz, 32-bit ARM926EJ-S 16 kB D-cache and 16 kB I-cache Memory Management Unit (MMU) Internal memory 192 kB embedded SRAM External memory interface NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only) 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM Security AES decryption engine (LPC3143 only) Secure one-time programmable memory for AES key storage and customer use 128 bit unique ID per device for DRM schemes Communication and connectivity High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY 2 Two I S interfaces Integrated master/slave SPI 2 Two master/slave I C-bus interfaces Fast UART Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA Four-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface System functions Dynamic clock gating and scaling Multiple power domainsLPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3143 only: secure booting using an AES decryption engine from SPI flash, NAND flash, SD/MMC cards, UART, or USB. DMA controller Four 32-bit timers Watchdog timer PWM module Master/slave PCM interface Random Number Generator (RNG) General Purpose I/O pins (GPIO) Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Operating voltage and temperature Core voltage: 1.2 V I/O voltages: 1.8 V, 3.3 V Temperature: 40 C to +85 C TFBGA180 package: 12 x 12 mm, 0.8 mm pitch 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC3141FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm SOT570-3 LPC3143FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12 12 0.8 mm SOT570-3 3.1 Ordering options Table 2. Ordering options for LPC3141/3143 2 Type number Core/bus Total Security High-speed USB 10-bit I S/ MCI Temperature 2 frequency SRAM engine ADC I C SDHC/ range AES channels SDIO/ CE-ATA LPC3141FET180 270/ 192 kB no Device/ 4 2 each yes 40 C to +85 C 90 MHz Host/OTG LPC3143FET180 270/ 192 kB yes Device/ 4 2 each yes 40 C to +85 C 90 MHz Host/OTG LPC3141 43 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 4 June 2012 2 of 69