LPC3180 16/32-bit ARM microcontroller hardware oating-point coprocessor, USB On-The-Go, and SDRAM memory interface Rev. 02 15 February 2007 Preliminary data sheet 1. General description The LPC3180 is an ARM9-based microcontroller for embedded applications requiring high performance combined with low power dissipation. It achieves these objectives through the combination of NXPs state-of-the-art 90 nanometer technology with an ARM926EJ-S CPU core with a Vector Floating Point (VFP) coprocessor and a large array of standard peripherals including USB On-The-Go. The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per ARM Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard architecture with separate 32 kB instruction and data caches, a demand paged MMU, DSP instruction extensions with a single cycle MAC, and Jazelle Java bytecode execution hardware. A block diagram of the microcontroller is shown in Figure 1. Power optimization in this microcontroller is done through process and technology development (Intrinsic Power), and architectural means (Managed Power). The LPC3180 also incorporates an SDRAM interface, NAND ash interfaces, USB 2.0 2 full-speed interface, seven UARTs, two I C-bus interfaces, two SPI ports, a Secure Digital (SD) interface, and a 10-bit ADC in addition to many other features. 2. Features 2.1 Key features n ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, running at up to 208 MHz. n 64 kB of SRAM. n High-performance multi-layer AHB bus system provides a separate bus for CPU data and instruction fetch, two data buses for the DMA controller, and another for the USB controller. n External memory interfaces: one supports DDR and SDR SDRAM, another supports single-level and multi-level NAND ash devices and can serve as an 8-bit parallel interface. n General purpose DMA controller that can be used with the SD card and SPI interfaces, as well as for memory-to-memory transfers. n USB 2.0 full-speed device, host (OHCI compliant), and OTG block. A dedicated PLL provides the 48 MHz USB clock. n Multiple serial interfaces, including seven UARTs, two SPI controllers, and two single 2 master I C-bus interfaces. n SD memory card interface.LPC3180 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface n Up to 55 GPI, GPO, and GPIO pins. Includes 12 GPI pins, 24 GPO pins, and six GPIO pins. n 10-bit ADC with input multiplexing from three pins. n Real-Time Clock (RTC) with separate power supply and power domain, clocked by a dedicated 32 kHz oscillator. Includes a 128 byte scratch pad memory. The RTC may remain active when the rest of the chip is not powered. n 32-bit general purpose high-speed timer with 16-bit pre-scaler with capture and compare capability. n 32-bit millisecond timer driven from the RTC clock. Interrupts may be generated using two match registers. n Watchdog timer. n Two PWM blocks with an output rate up to 50 kHz. n Keyboard scanner function provides automatic scanning of up to an 8 8 key matrix. n Standard ARM test/debug interface for compatibility with existing tools. n Emulation trace buffer with 2 k 24-bit RAM allows trace via JTAG. n On-chip crystal oscillator. n Stop mode saves power, while allowing many peripheral functions to restart CPU activity. n On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. n Boundary scan for simplied board testing. 3. Ordering information Table 1. Ordering information Type number Package Name Description Version 1 LPC3180FEL320 LFBGA320 plastic low prole ne-pitch ball grid array SOT824-1 package 320 balls body 13 13 0.9 mm 1 F = - 40 C to +85 C temperature range. LPC3180 2 NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 15 February 2007 2 of 36