LPC3220/30/40/50 16/32-bit ARM microcontrollers hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 2.1 24 June 2014 Product data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache and a 32 kB data cache. For low power consumption, the LPC3220/30/40/50 takes advantage of NXPs advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs, 2 2 two I C-bus interfaces, two SPI/SSP ports, two I S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. For additional documentation, see Section 15 References. 2. Features and benefits ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz. Vector Floating Point (VFP) coprocessor. 32 kB instruction cache and 32 kB data cache. Up to 256 kB of Internal SRAM (IRAM). Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory.LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time. External memory controller for DDR and SDR SDRAM as well as for static devices. Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices. Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources. Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be 2 used with the SD card port, the high-speed UARTs, I S-bus interfaces, and SPI interfaces, as well as memory-to-memory transfers. Serial interfaces: 10/100 Ethernet MAC with dedicated DMA Controller. USB interface supporting either device, host (OHCI compliant), or On-The-Go (OTG) with an integral DMA controller and dedicated PLL to generate the required 48 MHz USB clock. Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One of the standard UARTs supports IrDA. Three additional high-speed UARTs intended for on-board communications that support baud rates up to 921 600 when using a 13 MHz main oscillator. All high-speed UARTs provide 64 byte FIFOs. Two SPI controllers. Two SSP controllers. 2 2 Two I C-bus interfaces with standard open-drain pins. The I C-bus interfaces 2 support single master, slave, and multi-master I C-bus configurations. 2 Two I S-bus interfaces, each with separate input and output channels. Each channel can be operated independently on three pins, or both input and output channels can be used with only four pins and a shared clock. Additional peripherals: LCD controller supporting both STN and TFT panels, with dedicated DMA controller. Programmable display resolution up to 1024 768. Secure Digital (SD) memory card interface, which conforms to the SD Memory Card Specification Version 1.01. General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24 GP output pins, and 51 GP I/O pins. 10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from three pins. Optionally, the ADC can operate as a touch screen controller. Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator. NXP implemented the RTC in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. The RTC also includes a 32-byte scratch pad memory. 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer includes one external capture input pin and a capture connection to the RTC clock. Interrupts may be generated using three match registers. LPC3220 30 40 50 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.1 24 June 2014 2 of 80