LPC43S70 32-bit ARM Cortex-M4 + 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals, AES engine Rev. 1.3 10 January 2020 Product data sheet 1. General description The LPC43S70 are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for managing peripherals, 282 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer (SCTimer/PWM) and the Serial General Purpose I/O (SGPIO) interface, security features with AES engine, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC43S70 operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M4 with floating-point unit is often referred to as M4F. The LPC43S70 include an application ARM Cortex-M0 coprocessor and a second ARM Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The ARM Cortex-M0 core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with a simple instruction set and reduced code size. The Cortex-M0 does not support hardware multiply. 2. Features and benefits Main Cortex-M4 processor ARM Cortex-M4 processor, running at frequencies of up to 204 MHz. Built-in Memory Protection Unit (MPU) supporting eight regions. Built-in Nested Vectored Interrupt Controller (NVIC). Hardware floating-point unit. Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points. Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support. System tick timer. Cortex-M0 coprocessorNXP Semiconductors LPC43S70 32-bit ARM Cortex-M4/M0 microcontroller ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4 processor. Running at frequencies of up to 204 MHz. JTAG and built-in NVIC. Cortex-M0 subsystem ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on a separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM. Running at frequencies of up to 204 MHz. Connected via a core-to-core bridge to the main AHB multilayer matrix and the main ARM Cortex-M4 processor. JTAG and built-in NVIC. On-chip memory 264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kB of SRAM on the Cortex-M0 subsystem. Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually. 64 kB ROM containing boot code and on-chip software drivers. 64-bit of One-Time Programmable (OTP) memory for general-purpose use. Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage. One bank can store an encrypted key for decoding the boot image. AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API. Configurable digital peripherals Serial GPIO (SGPIO) interface. State Configurable Timer (SCT) subsystem on AHB. Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1. Serial interfaces Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second. 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2). One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY. One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY. USB interface electrical test software included in ROM USB stack. One 550 UART with DMA support and full modem interface. Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface. Two C CAN 2.0B controllers with one channel each. Use of C CAN controller excludes operation of all other peripherals connected to the same bus bridge. See Figure 1 and Ref. 1. Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. One SPI controller. LPC43S70 All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.3 10 January 2020 2 of 157