LPC55S2x/LPC552x 32-bit Arm Cortex -M33, CASPER, 256 KB SRAM 512 KB flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/ timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC, Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG Rev. 2.0 9 December 2020 Product data sheet 1. General description The LPC55S2x/LPC552x is an ARM Cortex-M33 based microcontroller for embedded applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption, high-speed and full-speed USB host and device interface with crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals 2 2 (which can be configured as a USART, SPI, high speed SPI, I C, or I S interface), Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC capable of simultaneous conversions, comparator, and temperature sensor. To support security requirements, the LPC55S2x/LPC552x also offers support for secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and TBSA compliance. 2. Features and benefits ARM Cortex-M33 core (r0p3): Running at a frequency of up to 150 MHz. Memory Protection Unit (MPU). ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities. System tick timer. The configuration of this instance includes MPU, FPU, DSP, ETM, and Trustzone. CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC). On-chip memory: Up to 512 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write. Up to 256 KB total SRAM consisting of 32 KB SRAM on Code Bus, 208 KB SRAM on System Bus (192 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use. NXP Semiconductors LPC55S2x/LPC552x 32-bit ARM Cortex-M33 microcontroller PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection, such as securing application code, and enabling secure flash update. On-chip ROM bootloader supports: Booting of images from on-chip flash Supports CRC32 image integrity checking. Supports flash programming through In System Programming (ISP) commands over following interfaces: USB0/1 interfaces using HID Class device, UART interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1) ROM API functions: Flash programming API, Power control API, and Secure firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files). Supports booting of images from PRINCE encrypted flash regions. Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096). Supports setting a sealed part to Fault Analysis mode through Debug authentication. Secure Boot support: Uses RSASSA-PKCS1-v1 5 signature of SHA256 digest as cryptographic signature verification. Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent). Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent). Uses x509 certificate format to validate image public keys. Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR). Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates revocations using Serial Number field in x509 certificate. Serial interfaces: Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7 and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected by software to be a USART, SPI, 2 2 I C, and I S interface. Each Flexcomm Interface includes a FIFO that supports 2 USART, SPI, and I S. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out 2 feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I S. 2 I C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true 2 I C pads also support high-speed Mode (3.4 Mbit/s) as a slave. USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library example in technical note (TN00063). USB 2.0 high-speed host/device controller with on-chip high-speed PHY. Digital peripherals: DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals. DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals. LPC55S2x/LPC552x All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 2.0 9 December 2020 2 of 131