LPC84x 32-bit Arm Cortex -M0+ microcontroller up to 64 KB flash and 16 KB SRAM FAIM memory 12-bit ADC 10-bit DACs Comparator Capacitive Touch Interface Rev. 2.1 28 October 2020 Product data sheet 1. General description The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and 16 KB of SRAM. 2 The peripheral complement of the LPC84x includes a CRC engine, four I C-bus interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins. For additional documentation related to the LPC84x parts, see Section 18. 2. Features and benefits System: Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port. Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. AHB multilayer matrix. Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported. Micro Trace Buffer (MTB). Memory: Up to 64 KB on-chip flash programming memory with 64 Byte page write and erase. Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on power-up. Code Read Protection (CRP) Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of SRAM can be used for MTB. Bit-band addressing supported to permit atomic operations to modify a single bit. ROM API support: Boot loader. Supports Flash In-Application Programming (IAP).NXP Semiconductors LPC84x 32-bit Arm Cortex-M0+ microcontroller 2 Supports In-System Programming (ISP) through USART, SPI, and I C. FAIM API. FRO API. On-chip ROM APIs for integer divide. Digital peripherals: High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits. High-current source output driver (20 mA) on four pins. High-current sink driver (20 mA) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function. CRC engine. DMA with 25 channels and 13 trigger inputs. Capacitive Touch Interface. Timers: One SCTimer/PWM with five input and seven output functions (including capture and match) for timing and PWM applications. Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 8 match/captures, 8 events, and 8 states. One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, external count, and DMA. Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input in the always-on power domain. Windowed Watchdog timer (WWDT). Analog peripherals: One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports two independent conversion sequences. Comparator with five input pins and external or internal reference voltage. Two 10-bit DACs. Serial peripherals: Five USART interfaces with pin functions assigned through the switch matrix and two fractional baud rate generators. Two SPI controllers with pin functions assigned through the switch matrix. 2 2 Four I C-bus interfaces. One I C supports Fast-mode Plus with 1 Mbit/s data rates 2 on two true open-drain pins and listen mode. Three I Cs support data rates up to 400 kbit/s on standard digital pins. Clock generation: LPC84x All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 2.1 28 October 2020 2 of 100