DOCUMENT NUMBER
9S12DJ64DGV1/D
MC9S12DJ64
Device User Guide
V01.20
Covers also
MC9S12D64, MC9S12A64, MC9S12D32,
MC9S12A32
Original Release Date: 19 Nov. 2001
Revised: 6 April 2005
Freescale Semiconductor, Inc.
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was
negligent regarding the design or manufacture of the part.
1Revision History
Version Revision Effective
Author Description of Changes
Number Date Date
16 NOV 19 NOV
V01.00 Initial version based on MC9SDP256-2.09 Version.
2001 2001
In table 7 I/O Characteristic of the electrical characteristics
18 FEB 18 FEB replaced tPULSE with tpign and tpval in linesPort ... Interrupt Input
V01.01
2002 2002 Pulse ltere andPort ... Interrupt Input Pulse passe
respectively.
TableOscillator Characteristic: removedOscillator start-up time
from POR or STO row
Table5V I/O Characteristic: Updated
Partial Drive IOH = +2mA and Full Drive IOH = 10mA
TableATD Operating Characteristic: Distinguish I for 1 and 2
REF
6 MAR 6 MAR
ATD blocks on
V01.02
2002 2002
TableATD Electrical Characteristic: Update C to 22 pF
INS
TableOperating Condition: Changed V and V to 2.35 V
DD DDPLL
(min)
Removed Document number except from Cover Sheet
Updated TableDocument Reference
Table5V I/O Characteristic : Corrected Input Capacitance to 6pF
Section:Device Pinou (112-pin and 80-pin): added in diagrams
RXCAN0 to PJ6 and TXCAN0 to PJ7
TablePLL Characteristic: Updated parameters K and f
4 June 4 June
1 1
V01.03
2002 2002
FigureBasic PLL functional diagra: Inserted XFC pin in diagram
Enhanced sectionXFC Component Selectio
Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode
Added 1L86D to TableAssigned Part ID number
Corrected MEMSIZ1 value in TableMemory size register
SubsectionDevice Memory Map: Removed Flash mapping from
$0000 to $3FFF.
4 July 4 July
V01.04 TableSignal Propertie: Added columnInternal Pull Resisto.
2002 2002
Preface TableDocument Reference: Changed to full naming for
each block.
TableInterrupt Vector Location, ColumnLocal Enabl:
Corrected several register and bit names.
FigureRecommended PCB Layout for 80QFP: Corrected
VREGEN pin position
Thermal values for junction to board and package
BGND pin pull-up
30 July 30 July Part Order Information
V01.05
2002 2002 Global Register Table
Chip Conguration Summary
Modied mode of Operations chapter
SectionPrinted Circuit Board Layout Proposal: added Pierce
Oscillator examples for 112LQFP and 80QFP