MCF52100CAE66 NXP

Freescale Semiconductor Document Number: MCF52110 Rev. 1, 3/2011 Data Sheet: Technical Data MCF52110 LQFP64 QFN64 MCF52110 ColdFire 10 mm x 10 mm 9mmx9mm Microcontroller MAPBGA81 LQFP100 Supports MCF52110 and 10 mm x 10 mm 14 mm x 14 mm MCF52100 The MCF52110 microcontroller family is a member of the Test access/debug port (JTAG, BDM) ColdFire family of reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF52110 microcontroller, focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 128 Kbytes of flash memory and 16 Kbytes of static random access memory (SRAM). On-chip modules include: V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal flash memory with Multiply Accumulate (MAC) Unit and hardware divider Three universal asynchronous/synchronous receiver/transmitters (UARTs) Two inter-integrated circuit (I2C) bus interface modules Queued serial peripheral interface (QSPI) module Eight-channel 12-bit fast analog-to-digital converter (ADC) with simultaneous sampling Four-channel direct memory access (DMA) controller Four 32-bit input capture/output compare timers with DMA support (DTIM) Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer Two 16-bit periodic interrupt timers (PITs) Real-time clock (RTC) module with 32 kHz crystal Programmable software watchdog timer Secondary watchdog timer with independent clock Interrupt controller capable of handling 57 sources Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2011. All rights reserved.Table of Contents 1 Family Configurations 3 2.4 Flash Memory Characteristics . 29 1.1 Block Diagram .4 2.5 EzPort Electrical Specifications 30 1.2 Features .4 2.6 ESD Protection 31 1.3 Reset Signals 20 2.7 DC Electrical Specifications . 31 1.4 PLL and Clock Signals .20 2.8 Clock Source Electrical Specifications 32 1.5 Mode Selection .20 2.9 General Purpose I/O Timing 33 1.6 External Interrupt Signals .21 2.10 Reset Timing 34 2 1.7 Queued Serial Peripheral Interface (QSPI) 21 2.11 I C Input/Output Timing Specifications 34 2 1.8 I C I/O Signals .21 2.12 Analog-to-Digital Converter (ADC) Parameters 36 1.9 UART Module Signals 22 2.13 Equivalent Circuit for ADC Inputs 37 1.10 DMA Timer Signals 22 2.14 DMA Timers Timing Specifications . 38 1.11 ADC Signals .22 2.15 QSPI Electrical Specifications . 38 1.12 General Purpose Timer Signals 23 2.16 JTAG and Boundary Scan Timing 38 1.13 Pulse Width Modulator Signals .23 2.17 Debug AC Timing Specifications . 41 1.14 Debug Support Signals .23 3 Mechanical Outline Drawings 42 1.15 EzPort Signal Descriptions 24 3.1 64-pin LQFP Package . 43 1.16 Power and Ground Pins 25 3.2 64 QFN Package . 46 2 Electrical Characteristics 26 3.3 81 MAPBGA Package . 50 2.1 Maximum Ratings .26 3.4 100-pin LQFP Package 52 2.2 Current Consumption 27 4 Revision History 54 2.3 Thermal Characteristics 28 MCF52110 ColdFire Microcontroller, Rev. 1 2 Freescale Semiconductor