Document Number: IMXRT1050CEC NXP Semiconductors Rev. 2, 03/2021 Data Sheet: Technical Data MIMXRT1051DVL6A MIMXRT1052DVL6A MIMXRT1051DVL6B MIMXRT1052DVL6B MIMXRT1051DVJ6B MIMXRT1052DVJ6B MIMXRT105SDVL6B i.MX RT1050 Crossover Processors Data Sheet for Consumer Products Package Information Plastic Package 196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch 196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch Ordering Information See Table 1 on page 5 1 i.MX RT1050 introduction The i.MX RT1050 is a new processor family featuring 1. i.MX RT1050 introduction 1 1.1. Features 2 NXPs advanced implementation of the Arm 1.2. Ordering information . 5 Cortex -M7 core, which operates at speeds up to 600 2. Architectural overview . 9 2.1. Block diagram 9 MHz to provide high CPU performance and best 3. Modules list 10 real-time response. 3.1. Special signal considerations . 16 3.2. Recommended connections for unused analog The i.MX RT1050 processor has 512 KB on-chip RAM, interfaces . 17 4. Electrical characteristics 19 which can be flexibly configured as TCM or 4.1. Chip-level conditions 19 general-purpose on-chip RAM. The i.MX RT1050 4.2. System power and clocks 26 integrates advanced power management module with 4.3. I/O parameters 31 4.4. System modules . 38 DCDC and LDO that reduces complexity of external 4.5. External memory interface . 43 power supply and simplifies power sequencing. The 4.6. Display and graphics 53 4.7. Audio 56 i.MX RT1050 also provides various memory interfaces, 4.8. Analog . 59 including SDRAM, RAW NAND FLASH, NOR 4.9. Communication interfaces 66 FLASH, SD/eMMC, Quad SPI, and a wide range of 4.10. Timers . 79 5. Boot mode configuration 81 other interfaces for connecting peripherals, such as 5.1. Boot mode configuration pins . 81 WLAN, Bluetooth, GPS, displays, and camera 5.2. Boot device interface allocation 81 6. Package information and contact assignments . 86 sensors. The i.MX RT1050 also has rich audio and video 6.1. 10 x 10 mm package information 86 features, including LCD display, basic 2D graphics, 6.2. 12 x 12 mm package information 98 camera interface, SPDIF, and I2S audio interface. The 7. Revision history . 110 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.i.MX RT1050 introduction i.MX RT1050 has analog interfaces, such as ADC, ACMP, and TSC. The i.MX RT1050 is specifically useful for applications such as: Industrial Human Machine Interfaces (HMI) Motor Control Home Appliance 1.1 Features The i.MX RT1050 processors are based on Arm Cortex-M7 Core Platform, which has the following features: Supports single Arm Cortex-M7 Core with: 32 KB L1 Instruction Cache 32 KB L1 Data Cache Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture Support the Armv7-M Thumb instruction set Integrated MPU, up to 16 individual protection regions Up to 512 KB I-TCM and D-TCM in total Frequency of 600 MHz Cortex M7 CoreSight components integration for debug Frequency of the core, as per Table 10,Operating ranges on page 21. The SoC-level memory system consists of the following additional components: Boot ROM (96 KB) On-chip RAM (512 KB) Configurable RAM size up to 512 KB shared with M7 TCM External memory interfaces: 8/16-bit SDRAM, up to SDRAM-166 8/16-bit SLC NAND FLASH, with ECC handled in software SD/eMMC SPI NOR/NAND FLASH Parallel NOR FLASH with XIP support Single/Dual channel Quad SPI FLASH with XIP support Timers and PWMs: Two General Programmable Timers (GPT) 4-channel generic 32-bit resolution timer Each support standard capture and compare operation Four Periodical Interrupt Timer (PIT) Generic 16-bit resolution timer Periodical interrupt generation i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021 2 NXP Semiconductors