RT600 Dual-core microcontroller with 32-bit Cortex -M33 and Xtensa HiFi4 Audio DSP CPUs Up to 4.5 MB SRAM FlexSPI with cache and dynamic decryption High-speed USB device/host + Phy 12-bit 1 Msamples/s ADC Analog Comparator Audio subsystems supporting up to 8 DMIC channels SDIO/eMMC AES/SHA/Crypto M33 coprocessor PUF key generation Rev. 1.9 30 December 2021 Product data sheet 1. General description The RT600 is a family of dual-core microcontrollers for embedded applications featuring an Arm Cortex-M33 CPU combined with a Cadence Xtensa HiFi4 advanced Audio Digital Signal Processor CPU. The Cortex-M33 includes two hardware coprocessors providing enhanced performance for an array of complex algorithms. The family offers a rich set of peripherals and very low power consumption. The Arm Cortex-M33 is a next generation core based on the ARMv8-M architecture that offers system enhancements, such as ARM TrustZone security, single-cycle digital signal processing, and a tightly-coupled coprocessor interface, combined with low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M33 CPU employs a 3-stage instruction pipe and includes an internal prefetch unit that supports speculative branching. A hardware floating-point processor is integrated into the core. On the RT600, the Cortex-M33 is augmented with two hardware coprocessors providing accelerated support for additional DSP algorithms and cryptography. The Cadence Xtensa HiFi 4 Audio DSP engine is a highly optimized audio processor designed especially for efficient execution of audio and voice codecs and pre- and post-processing modules. It supports four 32x32-bit MACs, some support for 72-bit accumulators, limited ability to support eight 32x16-bit MACs, and the ability to issue two 64-bit loads per cycle. There is a floating point unit providing up to four single-precision IEEE floating point MACs per cycle. The RT600 provides up to 4.5 MB of on-chip SRAM (plus an additional 128 KB of tightly-coupled HiFi4 ram) and several high-bandwidth interfaces to access off-chip flash. The FlexSPI flash interface supports two channels and includes an 32 KB cache and an on-the-fly decryption engine. The RT600 is designed to allow the Cortex-M33 to operate at frequencies of up to 300 MHz and the HiFi4 DSP to operate at frequencies of up to 600 MHz. 1.1 Peripherals The peripheral complement includes an FlexSPI flash interface with two channels, two SDIO/eMMC interfaces, a high-speed USB device/host with on-chip PHY, a 12-bit, 1 MSamples/sec ADC with temperature sensor, an analog comparator, AES256 and Hash engines with Physical Unclonable Function (PUF) key generation, a digital microphone NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs interface supporting up to eight channels and Voice Activation Detect, one I3C interface, one high-speed SPI interface and seven configurable serial interfaces that can be configured as a USART, SPI, I2C or I2S bus interface, each including a FIFO. When configured as USARTs the serial interfaces have the option to operate in deep-sleep mode using the 32 kHz oscillator or an external clock. There is a dedicated fractional baud rate generator for each of the serial interfaces. Timing peripherals include one advanced, 32-bit SCTimer/PWM module, five general purpose 32-bit timer/counters with PWM capability, a 24-bit, multiple-channel multi-rate timer, two windowed watchdog timers, a system tick timer with capture capability, and a Real-time clock module with independent power and a dedicated oscillator. A common OS Event Timer is provided for synchronized event generation and timestamping between the two CPUs. There are two general purpose DMA engines which can service most of the peripherals described in this section. The two DMA engines may be assigned to different CPUs and/or one may be used for secure operations, the other for non-secure. Mailboxes and hardware semaphores are provided to facilitate inter-core communication. A variety of oscillators and PLLs are available as clock sources throughout the system. 1.2 Shared system SRAM The entire system SRAM space of up to 4.5 MB is divided into up to 30 separate partitions, which are accessible to both CPUs, both DMA engines, and all other AHB bus masters. The HiFi4 CPU accesses the RAM via a dedicated 256-bit interface. Cache (with single-cycle access) is provided on this interface to improve performance. All other masters, including the Cortex-M33 processor and the DMA engines, access RAM via the main 32-bit AHB bus. These accesses are all single-cycle. Hardware interface modules arbitrate access to each RAM partition between the HiFi4 and the AHB bus. Under software control, each of the 30 individual SRAM partitions can be used exclusively as code or as data, dedicated either CPU, or shared among the various masters. Each partition can be independently placed in a low-power retention mode or powered off entirely. In addition to the shared SRAM, a total of 128 KB (64 KB code, 64 KB data) of local, Tightly-Coupled Memory (TCM) is provided for the exclusive use of the HiFi4 DSP processor. Access to this memory is single-cycle. 2. Features and benefits Control processor core Arm Cortex-M33 processor, running at frequencies of up to 300 MHz. Arm TrustZone. Arm Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions Hardware Floating Point Unit (FPU). Arm Cortex-M33 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input. RT600 All information provided in this document is subject to legal disclaimers. NXP Semiconductors B.V. 2021. All rights reserved. Product data sheet Rev. 1.9 30 December 2021 2 of 163