MK10FN1M0VLQ12 NXP

Document Number K10P144M120SF3 NXP Semiconductors Rev. 7, 02/2018 Data Sheet: Technical Data K10P144M120SF3 K10 Sub-Family Supports the following: MK10FX512VLQ12, MK10FN1M0VLQ12, MK10FX512VMD12, MK10FN1M0VMD12 Key features Security and integrity modules Hardware CRC module to support fast cyclic Operating Characteristics redundancy checks Voltage range: 1.71 to 3.6 V 128-bit unique identification (ID) number per chip Flash write voltage range: 1.71 to 3.6 V Temperature range (ambient): -40 to 105C Human-machine interface Low-power hardware touch sensor interface (TSI) Performance General-purpose input/output Up to 120 MHz Arm Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per Analog modules MHz Four 16-bit SAR ADCs Programmable gain amplifier (PGA) (up to x64) Memories and memory interfaces integrated into each ADC Up to 1024 KB program flash memory on non- Two 12-bit DACs FlexMemory devices Four analog comparators (CMP) containing a 6-bit Up to 512 KB program flash memory on DAC and programmable reference input FlexMemory devices Voltage reference Up to 512 KB FlexNVM on FlexMemory devices 16 KB FlexRAM on FlexMemory devices Timers Up to 128 KB RAM Programmable delay block Serial programming interface (EzPort) Two 8-channel motor control/general purpose/PWM FlexBus external bus interface timers NAND flash controller interface Two 2-channel quadrature decoder/general purpose timers Clocks Periodic interrupt timers 3 to 32 MHz crystal oscillator 16-bit low-power timer 32 kHz crystal oscillator Carrier modulator transmitter Multi-purpose clock generator Real-time clock System peripherals Communication interfaces Multiple low-power modes to provide power Two Controller Area Network (CAN) modules optimization based on application requirements Three SPI modules Memory protection unit with multi-master Two I2C modules protection Six UART modules 32-channel DMA controller, supporting up to 128 Secure Digital Host Controller (SDHC) request sources Two I2S modules External watchdog monitor Software watchdog Low-leakage wakeup unit NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Ordering parts.......................................................................................3 6.1.1 Debug trace timing specifications..................................21 1.1 Determining valid orderable parts............................................... 3 6.1.2 JTAG electricals.............................................................22 2 Part identification................................................................................. 3 6.2 System modules........................................................................... 25 2.1 Description...................................................................................3 6.3 Clock modules............................................................................. 25 2.2 Format..........................................................................................3 6.3.1 MCG specifications........................................................25 2.3 Fields............................................................................................3 6.3.2 Oscillator electrical specifications................................. 27 2.4 Example....................................................................................... 4 6.3.3 32 kHz oscillator electrical characteristics.....................29 3 Terminology and guidelines.................................................................4 6.4 Memories and memory interfaces................................................30 3.1 Definitions................................................................................... 4 6.4.1 Flash (FTFE) electrical specifications........................... 30 3.2 Examples......................................................................................4 6.4.2 EzPort switching specifications..................................... 34 3.3 Typical-value conditions..............................................................5 6.4.3 NAND flash controller specifications............................35 3.4 Relationship between ratings and operating requirements.......... 5 6.4.4 Flexbus switching specifications....................................38 3.5 Guidelines for ratings and operating requirements......................6 6.5 Security and integrity modules.................................................... 41 4 Ratings..................................................................................................6 6.6 Analog..........................................................................................41 4.1 Thermal handling ratings............................................................. 6 6.6.1 ADC electrical specifications.........................................41 4.2 Moisture handling ratings............................................................ 7 6.6.2 CMP and 6-bit DAC electrical specifications................49 4.3 ESD handling ratings................................................................... 7 6.6.3 12-bit DAC electrical characteristics............................. 51 4.4 Voltage and current operating ratings..........................................7 6.6.4 Voltage reference electrical specifications.....................54 5 General................................................................................................. 7 6.7 Timers.......................................................................................... 55 5.1 AC electrical characteristics........................................................ 8 6.8 Communication interfaces........................................................... 55 5.2 Nonswitching electrical specifications........................................ 8 6.8.1 CAN switching specifications........................................55 5.2.1 Voltage and current operating requirements..................8 6.8.2 DSPI switching specifications (limited voltage range)..56 5.2.2 LVD and POR operating requirements..........................9 6.8.3 DSPI switching specifications (full voltage range)........57 5.2.3 Voltage and current operating behaviors....................... 10 6.8.4 Inter-Integrated Circuit Interface (I2C) timing.............. 59 5.2.4 Power mode transition operating behaviors...................12 6.8.5 UART switching specifications..................................... 60 5.2.5 Power consumption operating behaviors....................... 13 6.8.6 SDHC specifications...................................................... 60 5.2.6 EMC radiated emissions operating behaviors................16 6.8.7 I2S/SAI switching specifications................................... 61 5.2.7 Designing with radiated emissions in mind................... 17 6.9 Human-machine interfaces (HMI)...............................................68 5.2.8 Capacitance attributes.................................................... 17 6.9.1 TSI electrical specifications........................................... 68 5.3 Switching specifications.............................................................. 17 7 Dimensions...........................................................................................69 5.3.1 Device clock specifications............................................17 7.1 Obtaining package dimensions.................................................... 69 5.3.2 General switching specifications....................................18 8 Pinout................................................................................................... 69 5.4 Thermal specifications.................................................................19 8.1 Pins with active pull control after reset....................................... 69 5.4.1 Thermal operating requirements.................................... 19 8.2 K10 Signal Multiplexing and Pin Assignments...........................70 5.4.2 Thermal attributes.......................................................... 20 8.3 K10 pinouts..................................................................................76 6 Peripheral operating requirements and behaviors................................ 21 9 Revision History...................................................................................78 6.1 Core modules............................................................................... 21 K10 Sub-Family, Rev. 7, 02/2018 2 NXP Semiconductors