NXP Semiconductors K80P121M150SF5 Data Sheet: Technical Data Rev. 5, 11/2016 Kinetis K80 Sub-Family MK80FN256VLL15 High performance ARM Cortex-M4F MCU with up to MK80FN256VDC15 256KB of Flash, 256KB of SRAM, Full Speed USB MK80FN256VLQ15 connectivity, and QuadSPI for interfacing to Serial NOR MK80FN256CAx15 flash The K80 sub-family extends Kinetis products with new features including QuadSPI serial flash interface and separate voltage domain for a sub-set of IO pins. The QuadSPI interface supports connections to Non-Volatile Memory for data or code. The 121 XFBGA (DC) 100 LQFP (LL) extended memory resources allow developers to enhance their 8 x 8 x 0.5 mm Pitch 14 x 14 x 1.7 Pitch embedded applications with greater capability and features. 0.65 mm 0.5mm Software compatibility with previous Kinetis devices ensures quick transitions from other Kinetis subfamilies. Enhancements include High Speed RUN for greater performance, and smart Peripherals like LPUART which can operate in STOP modes. 144 LQFP (LQ) 121 WLCSP (Ax) 20 x 20 x 1.6 Pitch 0.5 4.64 mm x 4.53 mm mm Performance Analog modules Up to 150 MHz ARM Cortex-M4 based core with DSP One 16-bit SAR ADCs, two 6-bit DAC and one instructions and Single Precision Floating Point unit 12-bit DAC Two analog comparators (CMP) containing a Memories and memory expansion 6-bit DAC and programmable reference input Up to 256 KB program flash with 256 KB RAM Voltage reference 1.2V FlexBus external bus interface and SDRAM controller Dual QuadSPI with OTF decryption and XIP Operating Characteristics 32 KB Boot ROM with built in bootloader Main VDD Voltage and Flash write voltage Supports SDR and DDR serial flash and octal configurations range:1.71V3.6 V Temperature range (ambient): -40 to 105C System and Clocks Independent V for PORTE (QuadSPI): DDIO Multiple low-power modes 1.71V3.6 V Memory protection unit with multi-master protection 3 to 32 MHz main crystal oscillator Communication interfaces 32 kHz low power crystal oscillator USB full-/low-speed On-the-Go controller 48 MHz internal reference Secure Digital Host Controller (SDHC) and FlexIO Timers One I2S module, three SPI, four I2C modules One 4 ch-Periodic interrupt timer and five LPUART modules Two 16-bit low-power timer PWM modules Two 8-ch motor control/general purpose/PWM timers Security Two 2-ch quadrature decoder/general purpose timers Hardware random-number generator Real-time clock with independent 3.3V power domain Supports DES, AES, SHA accelerator (CAU) Programmable delay block Multiple levels of embedded flash security Human-machine interface Low-power hardware touch sensor interface (TSI) General-purpose input/output NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Ordering Information Part Number Memory Maximum number of I O s Flash SRAM MK80FN256VLL15 256 KB 256 KB 66 MK80FN256VDC15 256 KB 256 KB 87 1 MK80FN256CAx15R 256 KB 256 KB 87 2 MK80FN256VLQ15 256 KB 256 KB 102 1. The 121-pin WLCSP package for this product is not yet available, however it is included in a Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more details. 2. The 144-pin LQFP package for this product is not yet available, however it is included in a Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more details. Device Revision Number Device Mask Set Number SIM SDID REVID JTAG ID Register PRN 1N03P 0001 0001 Related Resources Type Description Resource Product The Product Selector lets you find the right Kinetis part for your design. K-Series Product Selector Selector Fact Sheet The Fact Sheet gives overview of the product key features and its uses. K8x Fact Sheet 1 Reference The Reference Manual contains a comprehensive description of the K80P121M150SF5RM Manual structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal This document. connections. 1 Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis K 1N03P a particular device mask set. Package Package dimensions are provided in package drawings. LQFP 100-pin: 1 drawing 98ASS23308W XFBGA 121-pin: 1 98ASA00595D LQFP 144-pin: 2 98ASS23177W WLCSP 121-pin: Under 2 development 1. To find the associated resource, go to