NXP Semiconductors KE1xZP48M48SF0 Data Sheet: Technical Data Rev. 3, 06/2020 Kinetis KE1xZ with up to 64 KB MKE1xZ64VLF4 MKE1xZ64VLD4 Flash MKE1xZ64VFP4 Up to 48 MHz Arm Cortex-M0+ Based Microcontroller MKE1xZ32VLF4 MKE1xZ32VLD4 Providing up to 64 KB flash, up to 8 KB RAM, and a complete set MKE1xZ32VFP4 of analog/digital features, KE1xZ64 offers a robust Touch Sense Interface (TSI) and CAN bus for industrial networking, which provides high-level stability and accuracy in customer s home appliance touch UI and industrial control systems. 48 LQFP (LF) 44 LQFP (LD) 7x7x1.4 mm P 0.5 10x10x1.4 mm P 0.8 40 QFN (FP) 5x5x0.85 mm P 0.4 Core Processor and System Memory and memory interfaces Arm Cortex -M0+ core, supports up to 48 MHz Up to 64 KB program flash frequency Up to 8 KB SRAM Arm Core based on the ARMv6 Architecture and 64 Bytes flash cache Thumb -2 ISA Mixed-signal analog Configurable Nested Vectored Interrupt Controller 1 12-bit analog-to-digital converter (ADC) with up (NVIC) to 16 channel analog inputs per module, up to 1 Memory-Mapped Divide and Square Root module Msps (MMDVSQ) 1 high-speed analog comparators (CMP) with Reliability, safety and security internal 8-bit digital to analog converter (DAC) Cyclic Redundancy Check (CRC) generator module Timing and control 128-bit unique identification (ID) number 2 Flex Timers (FTM) for PWM generation, offering Internal watchdog (WDOG) with independent clock 6ch+2ch source 1 16-bit Low-Power Timer (LPTMR) with flexible External watchdog monitor (EWM) module wake up control ADC self calibration feature 1 Programmable Delay Block (PDB) with flexible On-chip clock loss monitoring trigger system Power management 1 32-bit Low-power Periodic Interrupt Timer (LPIT) Low-power Arm Cortex-M0+ core with excellent energy with 2 independent channels efficiency Real timer clock (RTC) Power management controller (PMC) with multiple power modes: Run, Wait, Stop, VLPR, VLPW and Debug functionality VLPS Serial Wire Debug (SWD) debug interface Debug Watchpoint and Trace (DWT) Micro Trace Buffer (MTB) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Supports clock gating for unused modules, and specific peripherals remain working in low power modes POR, LVD/LVR Connectivity and communications interfaces 3 low-power universal asynchronous receiver/ transmitter (LPUART) modules with FIFO support Clock interfaces and low power availability OSC: high range 4 - 40 MHz (with low power or high- 1 low-power serial peripheral interface (LPSPI) gain mode) and low range 32 - 40 kHz (with high-gain modules with FIFO support and low power mode only) availability 48 MHz high-accuracy (up to 1%) fast internal 1 low-power inter-integrated circuit (LPI2C) reference clock (FIRC) for normal Run modules with FIFO support and low power 8 MHz / 2 MHz high-accuracy (up to 3%) slow internal availability reference clock (SIRC) for low-speed Run 1 CAN module (MSCAN), with 5 Rx buffers and 3 128 kHz low power oscillator (LPO) Tx buffers Low-power FLL (LPFLL) Up to 50 MHz DC external square wave input clock Operating Characteristics System clock generator (SCG) Voltage range: 2.7 to 5.5 V Real time counter (RTC) Ambient temperature range: 40 to 105 C Human-machine interface (HMI) Supports up to 32 interrupt request (IRQ) sources Up to 42 GPIO pins with interrupt functionality Touch sensing input (TSI) module Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its uses. KE1xZ Family Fact Sheet 1 Product Brief The Product Brief contains concise overview/summary information to KE1xZ64PB enable quick evaluation of a device for design suitability. 1 Reference The Reference Manual contains a comprehensive description of the KE1xZP48M48SF0RM Manual structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal This document: connections. KE1xZP48M48SF0 1 Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis E 0N16X a particular device mask set. Package Package dimensions are provided in package drawings. 48-LQFP: 98ASH00962A drawing 44-LQFP: 98ASS23225W 40-QFN: 98ASA01371D 1. To find the associated resource, go to